Patent Application
20240310590
Various embodiments of this application relate to fabricating, integrating, and optically connecting active chip having active layer such as laser diode or optical amplifier chips, and in particular, photonic wire bonding of such optical element (e.g., laser diode chips, optical amplifier chips, etc.) to optical waveguides.
In optical telecommunication applications, optical sources are optically connected to optical fibers, on-chip integrated waveguides, or other optical devices. Typically, the optical source and optical devices are fabricated on separate chips having different material compositions. Low loss optical power transfer between such optical sources and receiving optical devices fabricated on separate chips is important for supporting high quality data transfer.
Various methods and designs described herein, may be used to fabricate laser or optical amplifier chips and/or optically connect them to optical devices using polymer waveguides (e.g., photonic wires) fabricated using photonic wire bonding. For example, a laser or an optical amplifier chip may be designed to facilitate optically connecting an active waveguide of the laser chip or the optical amplifier chip to a waveguide of the optical device where the laser chip or the optical amplifier chip is mounted p-side down on the carrier chip, e.g., to improve thermal transport from an active layer of the optical amplifier or laser chip to the carrier chip.
In some aspects, the techniques described herein relate to an optical system including an active optical chip optically connected to an optical device via a photonic wire, wherein the active optical chip is mounted on a carrier chip, the active optical chip including: a substrate layer; an active layer between the substrate layer and the carrier chip, wherein a major surface of the active layer includes an edge region; and an active waveguide within the active layer, the active waveguide having an active port closer to the edge region, the active port connected to a first end of the photonic wire, wherein the active waveguide is extended in a longitudinal direction from the active port away from active port; wherein a thickness of an end of the carrier chip closer to the active port or a thickness of the substrate layer above the edge region is configured to allow a waist of a focused light beam to be positioned at the active port without optically interfering with any portion of the carrier chip or the substrate layer, respectively.
In some aspects, the techniques described herein relate to an optical system including an active optical chip optically connected to an optical device via a photonic wire, wherein the active optical chip and the optical device are mechanically connected to a common frame, the active optical chip including: a substrate layer; an active layer between the substrate layer and a carrier chip; and an active waveguide within the active layer, the active waveguide having an active port attached to a first end of the photonic wire, wherein the active waveguide is extended in a longitudinal direction from the active port away from the active port; wherein a thickness of an end region of the carrier chip closer to the active port is configured to allow a waist of a focused light beam to be positioned at the active port without optically interfering with any portion of the carrier chip or the substrate layer.
In some aspects, the techniques described herein relate to a method of fabricating an optical assembly, the method including: providing an active photonic chip having an active layer and a substrate; providing a fiber optic array; mounting the active photonic chip on a tailored carrier chip such that the active layer is between the substrate and the carrier chip; mechanically connecting the carrier chip and the fiber optic array to a common frame; and optically connecting active waveguides of the active layer to the optical fibers of the optical fiber array by fabricating photonic wires between individual active waveguides and individual optical fibers.
In the following description of the various embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration various embodiments of the device. It is to be understood that other embodiments may be utilized and structural changes may be made.
Although certain preferred embodiments and examples are disclosed below, inventive subject matter extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses and to modifications and equivalents thereof. Thus, the scope of the claims appended hereto is not limited by any of the particular embodiments described below. For example, in any method or process disclosed herein, the acts or operations of the method or process may be performed in any suitable sequence and are not necessarily limited to any particular disclosed sequence. Various operations may be described as multiple discrete operations in turn, in a manner that may be helpful in understanding certain embodiments; however, the order of description should not be construed to imply that these operations are order dependent. Additionally, the structures, systems, and/or devices described herein may be embodied using a variety of techniques including techniques that may not be described herein but are known to a person having ordinary skill in the art. For purposes of comparing various embodiments, certain aspects and advantages of these embodiments are described. Not necessarily all such aspects or advantages are achieved by any particular embodiment. Thus, for example, various embodiments may be carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other aspects or advantages as may also be taught or suggested herein. It will be understood that when an element or component is referred to herein as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present therebetween. For clarity of description, “reflector” or “mirror” can be used interchangeably to refer to an optical element and/or a surface having a reflectivity greater than or equal to about 5% and less than or equal to 100%. For example, an optical element and/or a surface having a reflectivity greater than or equal to about 5% and less than or equal to 99%, greater than or equal to about 10% and less than or equal to 90%, greater than or equal to about 15% and less than or equal to 80%, greater than or equal to about 20% and less than or equal to 70%, greater than or equal to about 30% and less than or equal to 60%, or any value in any range/sub-range defined by these values can be considered as a reflector or mirror. It will be understood that “light having single wavelength”, “light beam having single wavelength”, “laser light having single wavelength”, “single wavelength light” or “single wavelength laser light”, can be light comprising wavelengths within a continuous wavelength or frequency band (e.g., a narrowband) centered at a center wavelength (or center frequency).
In some cases, a light source (e.g., a semiconductor laser) or an optical amplifier fabricated on a chip, may be optically connected to an optical device (e.g., an optical device fabricated on another chip), using a coupling waveguide (chip-to-chip coupling waveguide). In some cases, a first end of the coupling waveguide can be connected to a facet or port (e.g., output port or output facet) of the light source and a second end of the coupling waveguide can be connected to a facet or a port (e.g., input port or input facet) of a waveguide of the optical device (herein referred to as device waveguide). In some cases, the coupling waveguide can be an individually fabricated polymer waveguide. In some such cases, a polymer waveguide can be an in-situ structured waveguide. For example, a polymer waveguide may be structured using additive three-dimensional nanofabrication techniques. In particular, in some cases the polymer waveguide may be a directly written (e.g., using a light or a focused light beam) polymer waveguide commonly referred to as a photonic wire waveguide or photonic wire (PW). Such photonic wires may be air-cladded. In some cases, after fabrication, an air-cladded photonic wire may be embedded in a low index cladding material (e.g., a low index polymer) having a lower index of refraction than the photonic wire waveguide. In some cases, a photonic wire may be a freeform waveguide with customized shape and cross-section. In some such cases, at least a portion of the photonic wire can be a single mode waveguide. A photonic wire (PW) may enable highly efficient optical power transfer from the output port of the light source to the input port of the device waveguide, while allowing a distance and a high degree of misalignment between, e.g., an output port of a light source and an input port of the optical device. For example, the photonic wire may transmit 10% to 30%, 30% to 50%, 50% to 70%, 70% to 80%, or 80% to 99%, or 99.9 to 99.99% of the optical power output via the output port of the light source to the input port of the optical device, or any range formed by any of these values, while the output port of the light source and the input port of the optical device are separated by a distance (e.g., a lateral or longitudinal distance) between 10-30 microns, 30-50 microns, 50-100 microns, 100-150 microns, 150-200 microns, 200-500 microns, or any range formed by any of these values or may be possibly longer or shorter.
A directly written polymer waveguide or photonic wire can have a diameter (e.g., an average diameter) between 0.5 to 1 microns, 1 to 2 microns, 2 to 4 microns or any range formed by any of these values.
In some implementations, a directly written polymer waveguide may be polymer waveguide formed by three-dimensional photolithography using a precisely controlled focused laser beam.
In some cases, an optical output mode of the light source (e.g., laser diode) can be different from an optical mode supported by the input port of the device waveguide and the PW may be shaped to support highly efficient optical power transfer from the light source to the device waveguide. For example, a shape of the first end of the PW connected to the output port of the light source may be tailored to support efficient optical coupling between the optical output port and the PW and a shape of the second end of the PW connected to the input port of the device waveguide may be tailored to support efficient optical coupling between the PW and the input port. In some such examples, a shape (e.g., a cross-sectional shape) of the PW may change along the length of the polymer waveguide to support low loss transmission of optical power from the first end to the second end of the PW.
Optical coupling to an optical amplifier using a PW may also be possible. Accordingly, in any of the examples and/or configurations described above or elsewhere herein, the light source can instead be another type of active optical element such as an optical amplifier. For example, light may be coupled into the optical amplifier by a PW. Likewise, other optical elements having active layers may also be employed in place of a semiconductor laser or a semiconductor optical amplifier.
In some cases, fabrication of PWs between closely spaced optical devices and/or at the optical ports that are located within or below structures that can block or optically distort at least a portion of a focused laser beam used for fabricating the PW can be challenging. For example, when the active layer of an optical source or an optical amplifier is bonded to a substrate to improve heat dissipation from the active layer, a substrate layer above the active layer may not allow unobstructed optical access to an optical port of the corresponding active waveguide for connecting a PW to the optical port. In various implementations, an optical port may comprise a facet, e.g., a cleaved facet, or an end of a waveguide configured to couple light into or out of the waveguide. Various optical devices and structures disclosed herein are designed to enable fabricating and/or connecting a PW at an output port that is located very close to the surface of a substrate and/or below a thick dielectric structure. For example, the output face of a laser chip in various implementations described herein has its p-side or optical gain active layer bonded, e.g., directly bonded, to a carrier (e.g., to facilitate heat transport to the from the optical mode region to the carrier).
In some examples, the active chip 101 may comprise a substrate layer 118 and an active layer 111 disposed (e.g., grown) on the substrate layer 118. The active layer 111 may comprise an optical gain layer that can provide optical gain upon being pumped (e.g., by an injection current). The optical gain layer may comprise one or more semiconductor material such as a compound semiconductor material (e.g., a III-V material or layers of materials such as GaAs, InP, AlGaAs, InGaAsP, GaN, AlGaN, AlSb, and the like). The substrate layer 118 may comprise one or more semiconductor material, e.g., a semiconductor material on which the active layer 111 can be grown, including substrates that may not be lattice matched to the material, such as Si, SiC or Sapphire. The active layer 111 may include an active waveguide 114 within which light (e.g. laser light) is generated and/or amplified. In some cases, e.g., when the active chip comprises a laser, the active waveguide 114 may comprise an optical cavity or may be configured to provide optical feedback. For example, in some designs, the active waveguide 114 may include a distributed Bragg grating (DFB), a distributed Bragg mirrors (DBR), a reflective facet, a sampled grating distributed Bragg reflector (SGDBR), and the like. An active port (e.g., output port) 106 of the active waveguide 114 can be a facet (e.g., a cleaved facet) of the active waveguide 114, or an end of the waveguide 114 configured to couple light into or out of the active waveguide 114. In some cases, light generated and/or amplified within the waveguide 114 is output via the active port 106. In some other cases, the active waveguide 114 may receive light generated by another source via the active port 106. For example, when the active chip 101 comprises an optical amplifier, the active waveguide 114 may receive light generated by another optical device (e.g., the optical device 102). It should be understood that while in some of the implementations disclosed below the active chip 101 is referred to as the laser chip 101, in various implementations, the active chip 101 may comprise one or both of a light source or an optical amplifier. The optical source may comprise a laser (e.g., a semiconductor laser) or another optical source (e.g., an incoherent source of light such as a light emitting diode or LED). The laser and the LED may comprise semiconductor and/or non-semiconductor materials. The optical amplifier may comprise a semiconductor optical amplifier (SOA) or other type of optical amplifiers. In some cases, the active chip 101 may comprise a plurality of light sources (e.g., lasers) and/or a plurality of optical amplifiers. For example, the active chip 101 may comprise a laser array and/or an optical amplifier array.
The optical device 102 may comprise a device waveguide 115 disposed, formed, or embedded in a waveguide layer 112. In some cases, the waveguide layer 112 may be disposed, or formed on a device substrate 121 (e.g., a waveguide of a monolithically fabricated optical device). An device port (e.g., an input port) 103 of the device waveguide 115 can be a facet (e.g., a cleaved facet) of the device waveguide 115, or an end of the device waveguide 115 configured to couple light into or out of the device waveguide 115.
In some implementations the optical device 102 can be a silicon photonic PIC chip and the device waveguide 115 can be a silicon-on-insulator (SOI) waveguide. The device chip (optical device) 102 can be a silicon photonic PIC chip and the device waveguide 115 can be a silicon-on-insulator (SOI) waveguide.
The laser chip 101 and the device chip 102 may be mounted on or bonded to an optical bench or carrier chip 117. In various implementations, the optical device 102 can be an active or passive optical device. Accordingly, the device waveguide 115 may be a passive waveguide or an active waveguide that can provide optical gain. In the configuration shown in
In some implementations, the active chip 101 and the optical device 102 may be mounted such that a distance G between the active port 106 and the device port 103 along a longitudinal direction (e.g., parallel to the active waveguide 114 and the device waveguide 115 or along z-axis) is larger than 10 microns, 20 microns, 50 microns, or 100 microns, 200 microns, 500 microns or any range between any of the values or longer or shorter. In some cases, the distance G may be between 10 microns and 50 microns, 50 microns and 100 microns, or 100 microns and 150 microns, 150 microns and 200 microns, 200 microns and 500 microns or any range formed by these values or larger or smaller lower.
In some implementations, a vertical distance X1 (perpendicular to the top surface of the carrier chip 117) between a center of the active port 106 and a top surface of the carrier chip 117, is different than a vertical distance X2 between a center of the device port 103 and a top surface of the carrier chip 117. In some cases, X1 and X2 may from 5 to 30 microns, from 30 to 60 microns, from 60 to 100 microns or any value in a range formed by these values or longer or shorter.
The active port 106 may be optically connected to the device port 103 by a photonic wire (PW) 104 having a first end connected to the active port 106 and a second end connected to device port 103. In some cases, the PW 104 may be a curved waveguide having one or more curved regions which have different curvatures. In some cases, a shape of the first end of the PW 104 may be different than a shape of its second end. In some examples, the shape of the first end may be designed according to an optical mode of the active waveguide 114 and the shape of the second end may be designed according to the optical mode of the waveguide 115. In some cases, a shape and a cross-section of the PW 104 along its length may be designed to reduce optical transmission loss between the first and the second end (e.g., optical transmission loss causes by optical mode mismatch). In some cases, a diameter of the PW 104 may be between 1 and 2 microns, 2 and 4 microns, 4 and 5 microns, 5 and 6 microns, or any range between any of these values or larger or smaller. In some cases, a lateral cross section of the PW (perpendicular to a direction of propagation of light in the PW), comprises an elliptical shape. In some cases, the elliptical shape of the PW 104 may result in two perpendicular optical axes. In some cases, light having different polarization states may propagate at different velocities along the PW 104.
In some cases, the output facet 106 and/or the input port 103 may be coated with an antireflection (AR) layer(s) (e.g., including a plurality of dielectric layers). An AR layer may be designed to reduce optical reflection at an interface between a PW 104 and the device port (e.g., optical device port) 103 or the active port 106.
In some cases, the PW 104 may be bonded to the active port 106 (or the device port 103). For example, a bond (e.g., a chemical bond) may be formed between the output port 106 of the active waveguide 114 and the first end of the PW 104, and/or the input port 103 of the device waveguide 115 and the second end of the PW.
In some examples, the first or the second end of the PW 104 that is connected to the active port 106 (or the device port 103), may cover a portion of the active waveguide 114 (or the input waveguide 115). In some such examples, the first or the second ends of the polymer PW 104 may be conformably shaped according to a shape or size of the port 103, 106 and or waveguide 114, 115 to which they are connected to.
In various implementations, the PW 104 is fabricated using a photonic wire bonder after mounting the device chip 102 and the laser chip 101 on the optical bench (e.g., carrier chip) 117. In some cases, the PW 104 may be fabricated using three-dimensional photolithography such as using a focused laser beam 130 that can be moved in three dimensions to be located precisely in three dimensions. In some cases, the focused light beam 130 (e.g., a focused laser beam) may be output by a movable optical head 132 (e.g., a lens). In some cases, a wavelength of the focused light beam can be in a wavelength range (e.g., 700 nm to 900 nm) that can cure or cross-link a polymer used to fabricate the PW, for example, via a two-photon process. In some cases, a focal length f, e.g., a vertical distance (e.g., along x-axis) between the beam waist of the focused light beam 130 and the optical head 132 can be from 50 to 100 microns, from 100 to 200 microns, from to 200 to 300 microns, from to 300 to 500 microns, or any ranges formed by these values or smaller or larger values.
To fabricate the PW 104, a gap between the device chip 102 and the laser chip 101, may be filled with a photosensitive polymer. In some cases, a layer of photosensitive polymer may be disposed on at least a portion of device chip 102 and at least a portion of the active chip 101. In some cases, photosensitive polymer may comprise PMMA, PDMS, or other types of photosensitive polymers. Subsequently, the focused laser beam 130 may be used to polymerize selected regions of the photopolymer (e.g., via two-photon photo polymerization) according to a desired shape of the PW 104. The focused laser beam 130 may have a high numerical aperture. A position of the laser head (e.g., optical head) 132 and thereby the position of waist of the focused laser beam 130 may be controlled by several micro/nano-positioners is three dimensions. In some cases, the photopolymer may be baked at an elevated temperature before and/or after photopolymerization. In some examples, the PW 104 may be an air-cladded waveguide. In some examples, the PW 104 may be encapsulated in a polymer layer after fabrication.
When the active layer 111 of the active chip 101 is pumped (e.g., electrically pumped by an injection current), heat generated in the active layer 111 can be dissipated to the carrier chip via the substrate layer 118. In some cases, e.g., when the active layer 111 comprises high power laser or optical amplifier, heat transport via the substrate layer 118 to maintain the temperature of the active waveguide 114 within below a threshold value above which the performance of the active chip is degraded below an acceptable level. As such, in these cases, it can be desirable to mount the active chip 101 on the carrier chip 117 in a manner that the active layer 111 is closer, in thermal contact, or in direct contact with the carrier chip 117 so that the efficiency or heat transport from the active layer 111 to the carrier chip is increased and/or improved. In these cases, the active layer 111 can be between the substrate layer 118 and the carrier chip 117. For example, in some cases, the active layer 111 can be in thermal contact with the carrier chip 117 (e.g., via direct contact, a conductive layer and/or an intermediate layer). Given that typically the portion of the active layer 111 that is away from or on opposite side as the substrate layer 118 comprise a p-type material (e.g., a p-type semiconductor material), bonding or mounting the active chip 101 to the carrier chip 117 via the active layer 111 or layers thereon opposite the side of the active layer opposite the substrate 118 may be referred to as a p-side down configuration.
In addition to the substrate layer 118, given the short distance the waist of the focused light beam 130 and the top surface of the carrier chip 117, the carrier chip 117 may distort, disrupt and/or block at least a portion of the focused light beam 130 and reduce its intensity and/or the confinement (e.g., by diffracting and reflecting a portion of the focused light beam 130 below its waist.
In some cases, alternatively or in addition the carrier chip 117 may be patterned or tailored to reduce interference of the carrier chip 117 with the focused light beam 130 and/or allow optical access to a region near the active port 106 from below.
Accordingly, some of the active chip designs and the configurations disclosed below may be used to optically connect active optical devices (e.g., lasers and optical amplifier) that are mounted p-side down on carrier chip (for more efficient heat dissipation) to other devices mounted or formed on the carrier chip.
In various implementations, an area of the edge region A can be from 10 to 50 micrometer squared, from 50 to 150 micrometer squared, from 150 to 300 micrometer squared, or any ranges formed by these values or larger or smaller values. In some cases, A may be determined based at least in part on properties of the focused light beam 130 (e.g., a convergence angle, focal distance, and the like).
In some implementations, a width (W) of the edge region in a lateral direction (e.g., along y-axis) can be from 25% to 50% of D, from 50% to 75% of D, from 75% to 100% of D, from 100% to 150% of D, from 150% to 200% of D, or any ranges formed by these values or larger or smaller values.
In various implementations, the thickness D or the average thickness Dav can be from 50 to 75 microns, from 75 to 150 microns, from 150 to 200 microns, from 200 to 500 microns, or any ranges formed by these values or larger or smaller values.
In various implementations, the thickness t or the average thickness tav is from 0 to 1 micron, from 1 micron to 3 microns, from 3 microns to 10 microns, or any ranges formed by these values or larger or smaller values.
In various implementations, the length of the edge region (L) in the longitudinal direction can be from 25% to 50% of D, from 50% to 75% of D, from 75% to 100% of D, from 100% to 150% of D, from 150% to 200% of D, or any ranges formed by these values or larger or smaller values.
In various implementations, the lateral width (along or parallel to y-axis) of the edge region (W) in the lateral direction can be from 25 microns to 50 microns, from 50 microns to 100 microns, to from 100 microns to 500 microns, or any ranges formed by these values or larger or smaller values. In some examples, W may extend from lateral edge of the active layer 111 to an opposite lateral edge of the active layer 111. In these examples, W is substantially equal to a lateral width of the active layer 111 (Wc), and/or substantially equal to a lateral width of the active chip 101.
In some cases, the portion of patterned substrate layer 119 above the edge region is completely removed such that the edge region of the active layer 111 is exposed (t=tav=0).
In some implications, the patterned substrate layer 119 may be tailored or patterned according to a shape and size of the focused light beam 130 near its focal point.
In some cases, the thickness (t) or an average thickness (2Cav) of the substrate layer 119 above the edge region of the active layer 111 may vary along the lateral and/or the longitudinal direction.
In various implementations, the edge region can have a rectangular, square, circular, elliptical, or an irregular shape.
In some cases, the patterned substrate layer 119 may be formed starting from a non-patterned substrate layer 118 using lithographically patterned etch mask (e.g., a polymer mask) and etching (e.g., dry or wet etching). For example, first the non-patterned substrate layer 118 may be covered by a photoresist. Next, the photoresist may be lithographically patterned to remove the portion of the photoresist layer disposed above the edge region. Finally, a region of the substrate layer 111 above the edge region is etched to reduce the thickness of the substrate layer 111 to a desired value. In some cases, the patterned substrate layer 119 may comprise an etch stop layer 134 configured to be used to stop the etching process when the thickness or the average thickness of patterned substrate layer 119 above the edge region is reduced to the desired thickness.
In some cases, L, W, and/or A, may be determined such that less than 10%, less than 20%, or less than 30% (or a percentage or percentage range between or formed by any of these values), of the optical power of the focused beam of light 130 is incident on the patterned substrate layer 119 and thereby refracted, diffracted, scattered, or absorbed by the patterned substrate layer 119.
As mentioned above, in some implementations, the carrier chip 117 can be patterned or structured to further reduce obstruction, scattering, diffraction, refraction, attenuation, and/or distortion of the focused light beam 130.
In some cases, a thickness of a region of the structured carrier chip 116 between the optical device 102 and the active chip 101 may be reduced. In some cases, a length of the thin region of the structured carrier chip 116 along the longitudinal direction along z-axis can be substantially equal to a longitudinal distance (G) between the optical device 102 and the active chip 101. In some cases, the length of the thin region of the structured carrier chip 116 along the longitudinal direction along z-axis can be larger or smaller than a longitudinal distance (G) between the optical device 102 and the active chip 101. In some cases, a depth (H) of a cavity generated above the thin region can be from 5 to 10 microns, from 10 to 50 microns, from 50 to 150 microns, or any ranges formed by these values or larger or smaller values. H can be a vertical distance between a major top surface of the structured carrier chip 116 above which the optical device 102 (or the active chip 101) is mounted and the top surface 222 of the structured carrier chip 116 in the thin region.
In some examples, the active source 101 and the optical device 102 may be mounted on two separate carrier chips. The active chip 101 may be mounted p-side down on the corresponding carrier chip. In some such cases, the two separate carrier chips may be mechanically stabilized with respect to each other such that a spatial position of the active port 106 relative to the device port 103 is fixed. For example, both carrier chips may be attached to a common frame (e.g., as part of a connector assembly). In these cases, the carrier chip on which the active chip 101 is mounted may be patterned or structured to provide sufficient optical access to a region around the active port 106 such that a photonic wire 104 connected to the active port 106 can be fabricated using a focused light beam that is incident on the photonic wire bonding region from the bottom side of the carrier chip.
In some such examples, the optical device 102 to which the active chip 101 is optically connected via a photonic wire, may be positioned such that a major surface 140 of the device substrate 121 opposite to the surface on or within which the device waveguide 115 is formed, is on top and the device waveguide 115 is at the bottom side of the optical device 102. With continued reference to
With continued reference to
In various implementations, t (or fav) is smaller than 50% of the D (or Dav). The edge region 302 may have any shape and is extended from the edge of the active port 106 away from the edge along the longitudinal direction parallel to the active waveguide 114 (e.g., z-axis), and along the lateral direction (e.g., y-axis) away from the active waveguide 114 toward the opposite edges of the active layer 111. In various implementations, to prevent an interaction between the focused light beam 130 and the patterned substrate layer 119, a shape, a length (L) or an average length (Lav), and/or a width (W) or an average width (Wav) of the edge region 302 may configured or selected based at least in part on the focal distance (f) and/or a convergence or convergence angle of the focused light beam 130 used to fabricate the PW 104. In some cases, an angle of convergence of the focused beam of light (θ) is larger than 30 degrees, larger than 45 degrees, larger than 60 degrees, larger than 75 degrees, larger than 90 degrees, or larger than 105 degrees, or any range formed by any of these values or larger than any values between these values. In some cases, a shape, size, and/or an area of the edge region may be designed such that less than 10%, less than 20%, or less than 30% (or any percentage range formed by any of these values), of the optical power of the focused beam of light 130 is incident on the patterned substrate layer 119 and thereby refracted, diffracted, scattered, or absorbed by the patterned substrate layer 119.
The active chip 101 may further comprise a bottom electrode 407 (e.g., a first conductive layer) and a top electrode 123 (e.g., a second conductive layer) configured to provide an injection current to the active layer 111 in order to pump a region of the active layer 111 at and/or near the optical mode 402.
In some implementations, the top electrode 123 may be replaced by a second bottom electrode 406 that is connected to a conductive layer disposed between the active layer 111 and the patterned substrate layer 119 by vertical conducive line 404 (e.g., a conductive via).
In some implementations, the bottom surface 504 corresponding to the edge region 302 of the etched portion of the substrate layer (or the active layer 111) can be symmetrically or near symmetrically positioned with respect to the active waveguide 114. In some cases, a lateral distance (along z-axis) of an edge of the exposed bottom surface from the active waveguide 114 can be substantially equal to W/2. In some cases, a lateral distance (along z-axis) of two opposite edges of the bottom (major) surface, that define the width W, from the active waveguide 114 can be substantially equal to W/2. In some cases, W can be at least 5 times, 10 times, 20 time, or 100 times, larger than a width of the active waveguide 114 or any range formed by any of these values or possibly larger or smaller. In some cases, W can be determined based on D, for example, W can be from 50% of D to 100% of D, from 100% of D to 200% of D or any ranges formed by these values or larger or smaller. In some implementations, W, L, and/or A (the area of the edge region or etched region of the substrate), may be increased proportional to D, such that less than 10%, less than 20%, or less than 30% (or any percentage range formed by these values), of the optical power of the focused beam of light 130 is incident on the patterned substrate layer 119 and thereby refracted, diffracted, scattered, or absorbed by the patterned substrate layer 119.
In some cases, at least a portion of the top (major) surface of the patterned substrate 119 may comprise a conductive region. In some cases, the top surface of the patterned substrate 119 may comprised at least two alignment marks 502. These alignment marks 502 may be defined and fabricated using lithographic techniques (e.g., IR imaging) to align them with features on the bottom surface of p-side of the active chip 101. These alignment marks 502 may be used to control and position the focused light beam 130 with respect to the active port 106 to facilitate fabricating a portion of the PW 104 at or near the active port 106.
In some cases, the individual active chips 101 (e.g., 12 active chips in this case) having patterned substrate layers 119, may be separated from the wafer 520 by cleaving the wafer 520 along a lateral cleave line 508, and along longitudinal cleave lines 514.
In some implementations, an active chip 101 may include a vertical alignment hole configured to provide optical access to a region of the top (major) surface of its active layer 111. In some, cases the vertical alignment hole may be configured to allow determining a vertical distance (e.g., along or parallel to the x-axis) of the top surface of the active layer 111 from a reference point (e.g. a reference point on the optical head 132) and thereby enable or facilitate controlling the optical head 132 to position the waist of the focused light beam 130 near or at the active port 106, e.g., when direct imaging of the active port is difficult or not possible.
In these cases, the image (height information) obtained via the vertical alignment hole 602 may be used to position the waist of the focused light beam 130 at or near the active port 106 to forming and/or optically connecting the PW 104 to the active port 106.
In some cases, a vertical distance (d2) between a top (major) surface of the patterned substrate layer 119 above the edge region 302 and the bottom (major) surface of the active layer 111 can be from 0.5 to 1 micron, from 1 to 5 microns, from 5 to 15 microns, or any ranges formed by any of these values or possibly larger or smaller.
In some implementations, a lower bound for the thickness (t) or average thickness (fav) of the patterned substrate layer 119 above the edge region 302 may be limited by the mechanical stability of a portion of the active layer 111 below the edge region 302. For example, if t or tav is smaller than a threshold value, the portion of the active layer 111 below the edge region 302 may bend down or up due to internal mechanical stress that was previously balanced by the substrate layer 119. On the other hand, a thickness (t) or average thickness (tav) of the patterned substrate layer 119 above the edge region 302 that provides sufficient mechanical support to the portion of the active layer 111 below the edge region 302, may not provide sufficient optical access to active port 106 for fabrication of the 104 without interfering with the focused light beam 130.
In some implementations, a support layer (e.g., a polymer layer) may be disposed on a thin region of the patterned substrate layer 119 above the edge region 302, or above a region of the active layer 111 below the edge region 302, to mechanically support the region of the active layer 111 below the edge region 302 (e.g., when t or tav is smaller than a threshold value).
The support layer may comprise a first material having refractive index close to the refractive index of a second material used to fabricate the PW 104 to reduce or avoid optical distortion of the focused light beam 130 by diffraction or refraction near an interface between the first and the second materials. For example, a difference between the refractive index of the first and the second materials, can be less than 0.1%, less than 1%, less than 2%, less than 5%, less than 10% (or any range formed by any of these values), of the refractive index of the second material. Additionally, the support layer (first material) may have a low optical absorption at a wavelength of the focused light beam 130. In some cases, the support layer can be an optically transparent material that allows imaging the active port layer without significant optical distortion. In some cases, the support layer may comprise a polymer (e.g., a UV curable polymer) such as SU8.
In some cases, the support layer 702 may be disposed above at least a portion of the edge region of the active layer 711 and longitudinally extended from an un-etched region 713 of the patterned substrate layer 119 to an end, or close to an end, of the active chip 701 near the active port 106. A length 704 of the support layer 702 (e.g., along or parallel to the z-axis) can be from 25 microns to 50 microns, from 50 microns to 100 microns, from 100 microns to 500 microns, or any ranges formed by these values or possibly larger or smaller. Accordingly, a longitudinal distance 708 between an end of the support layer 702 near the active port 106 and the active port 106 can be from 0 to 10 microns, from 10 to 20 microns, from 20 to 50 microns, or any ranges formed by these values or possibly larger or smaller.
In some examples, a width of the edge region of the active layer 711 may have a width (W) substantially equal to a width (Wc) of the active chip 701. In some such examples, the width of the support layer 702 (along or parallel to the y-axis) can be substantially equal to the width of the edge region and the width of the active chip 701.
As mentioned above, the optical properties of the support layer 702 may be configured to allow imaging regions near or at the active port 106, and/or positioning the waist of the focused light beam 130 near the active port 106 without being distorted by the active layer 702 such that positioning cannot be performed. As such the focused light beam 130 may be used to fabricate the PW 104 in the presence of the support layer 702 (e.g., a polymer layer).
In the example shown, the wafer 720 can be divided into a plurality of lateral wafer sections where an individual lateral wafer section is defined by two consecutive longitudinal cleave lines 514, or a longitudinal cleave line and a lateral edge of the wafer. An individual lateral wafer section includes two active wafers and an etched region 712. In some cases, the lateral cleave line 508 may divide the individual lateral etched regions and the individual active waveguides 506 to first and second etched portions, and first and second waveguide portions. In some cases, the individual active chips (e.g., 12 active chips in this case) having a patterned substrate layer 119 mechanically supported by a support layer 702, 703, may be separated from the wafer 720 by cleaving the wafer 720 along a lateral cleave line 508, and along longitudinal cleave lines 514.
In some implementations, the active layer of the active chip 801 can be disposed between a substrate layer of the active chip 801 and the tailored carrier chip 802. In some such cases, the active layer of the active chip 801 may be in thermal contact with the tailored carrier chip 802 directly or via an intermediate layer (e.g., a conductive intermediate layer such as the conductive layer 124), and the tailored carrier chip 802 may be attached to a bottom section 814 of the optical assembly 800.
The optical fiber array 809 may comprise an optical fiber mount 804 comprising a V-groove array configured for aligning the plurality of optical fibers substantially parallel to a longitudinal direction (e.g., parallel to the z-axis). The optical fiber mount 804 may be attached to or mounted on a top section 816 of the optical assembly 800. An optical fiber of the plurality of optical fibers may comprise an optical fiber waveguide 808 (having a core and a cladding layer) and a buffer 810 around the optical fiber waveguide 808. A portion of the buffer 810 covering a section of the optical fiber waveguide 808 placed with a V-groove may be removed such that the optical fiber waveguide 808 is in direct contact with the V-groove.
In some implementations, the tailored carrier chip 802 may be attached to the top section 816 of the optical assembly 800, e.g., via a side wall of the tailored carrier chip 802 and an internal wall of the top section 816 of the optical assembly 800, the side wall and the internal wall being parallel to the x-z plane. In some such implementations, the bottom section 814 of the optical assembly 800 may be connected to the bottom (major) surface of the tailored carrier chip 802 after fabricating the photonic wires between the active waveguides and the optical fibers.
Some additional nonlimiting examples of embodiments discussed above are provided below. These should not be read as limiting the breadth of the disclosure in any way.
A major surface of a layer or chip (e.g., active layer, substrate layer, or carrier chip) can be a top surface or bottom surface of the layer or the chip where a thickness of the layer of the chip along a direction perpendicular to the major surface is smaller than a width or length of the major surface. The major surface can have a rectangular shape or any shape having a plurality of edges.
It should be understood that in various designs and implementations described above thermal contact includes direct contact, contact via one or more intermediate layers (e.g., metallic or dielectric layers), some of which can be thermally conductive layers.
Conditional language, such as “can,” “could,” “might,” or “may,” unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and/or steps. Thus, such conditional language is not generally intended to imply that features, elements, and/or steps are in any way required for one or more embodiments.
Conjunctive language such as the phrase “at least one of X, Y, and Z,” unless specifically stated otherwise, is to be understood within the context used in general to convey that an item, term, etc. may be either X, Y, or Z. Thus, such conjunctive language is not generally intended to imply that certain embodiments require the presence of at least one of X, at least one of Y, and at least one of Z.
Language of degree, as used herein, such as the terms “approximately,” “about,” “generally,” and “substantially,” represent a value, amount, or characteristic close to the stated value, amount, or characteristic that still performs a desired function or achieves a desired result. For example, the terms “approximately,” “about,” “generally,” and “substantially” may refer to an amount that is within +10% of, within +5% of, within +2% of, within +1% of, or within +0.1% of the stated amount. As another example, the terms “generally parallel” and “substantially parallel” refer to a value, amount, or characteristic that departs from exactly parallel by +10 degrees, by +5 degrees, by +2 degrees, by +1 degree, or by +0.1 degree, and the terms “generally perpendicular” and “substantially perpendicular” refer to a value, amount, or characteristic that departs from exactly perpendicular by +10 degrees, by +5 degrees, by +2 degrees, by +1 degree, or by +0.1 degree.
Various configurations have been described above. Although this invention has been described with reference to these specific configurations, the descriptions are intended to be illustrative of the invention and are not intended to be limiting. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention. Thus, for example, in any method or process disclosed herein, the acts or operations making up the method/process may be performed in any suitable sequence and are not necessarily limited to any particular disclosed sequence. Features or elements from various embodiments and examples discussed above may be combined with one another to produce alternative configurations compatible with embodiments disclosed herein. Various aspects and advantages of the embodiments have been described where appropriate. It is to be understood that not necessarily all such aspects or advantages may be achieved in accordance with any particular embodiment. Thus, for example, it should be recognized that the various embodiments may be carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other aspects or advantages as may be taught or suggested herein.
This application claims the benefit of priority of U.S. Provisional Application No. 63/490,081 titled “SEMICONDUCTOR LASER CHIP FOR PHOTONIC WIRE BONDING” (Docket No. FREDOM.036PR), which was filed on Mar. 14, 2023, the entire disclosure of which is expressly incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63490081 | Mar 2023 | US |
