Semiconductor light-emitting device and fabrication method thereof

Abstract

A semiconductor light-emitting device is disclosed. The semiconductor light-emitting device comprises a multilayer epitaxial structure disposed on a semiconductor substrate. The semiconductor substrate has a predetermined lattice direction perpendicular to an upper surface thereof, wherein the predetermined lattice direction is angled toward [0ī1] or [01ī] from [100], or toward [011] or [0 ii] from [ī00] so that the upper surface of the semiconductor substrate comprises at least two lattice planes with different lattice plane directions. The multilayer epitaxial structure has a roughened upper surface perpendicular to the predetermined lattice direction. The invention also discloses a method for fabricating a semiconductor light-emitting device.

Description

BRIEF DESCRIPTION OF DRAWINGS

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIGS. 1A to 1B are cross sections of an embodiment of a method for fabricating a semiconductor light-emitting device;

FIG. 1C is a magnified diagram showing a multilayer epitaxial structure of FIG. 1B;

FIG. 1D is a plan view SEM (scanning electron microscope) image of a multilayer epitaxial structure of FIG. 1B;

FIG. 2 is a magnified diagram showing a part of the semiconductor substrate shown in FIGS. 1A and 1B; and

FIGS. 3A and 3B show several lattice planes of a cubic crystal lattice structure, respectively.

Claims

1. A semiconductor light-emitting device, comprising: a semiconductor substrate having a predetermined lattice direction perpendicular to an upper surface thereof, wherein the predetermined lattice direction is oriented toward [0ī1] or [01ī] with a first angle from [100], or toward [011] or [0 ii] with a second angle from [ī00], so the upper surface of the semiconductor substrate comprises at least two lattice planes with different lattice plane directions; anda multilayer epitaxial structure disposed on the semiconductor substrate, wherein the multilayer epitaxial structure has a roughened upper surface perpendicular to the predetermined lattice direction.

2. The device as claimed in claim 1, wherein the multilayer epitaxial structure comprises an n-type semiconductor layer, a p-type semiconductor layer and an active layer interposed therebetween.

3. The device as claimed in claim 1, wherein the first or the second angle is between 6° and 55°.

4. The device as claimed in claim 1, wherein the first or the second angle is 15°.

5. The device as claimed in claim 1, wherein the roughened upper surface of the multilayer epitaxial structure has a roughening depth not less than 0.05 μm.

6. The device as claimed in claim 1, wherein the roughened upper surface of the multilayer epitaxial structure has a roughening depth between 0.05 μm and 1 μm.

7. The device as claimed in claim 1, wherein the upper surfaces of the multilayer epitaxial structure and the semiconductor substrate have substantially the same surface topography.

8. The device as claimed in claim 1, wherein the lattice direction is defined by having a group III atom located at the [000] position of the coordinate of the unit cell as the origin.

9. A method for fabricating a semiconductor light-emitting device, comprising: providing a semiconductor substrate having a predetermined lattice direction perpendicular to an upper surface thereof, wherein the predetermined lattice direction is oriented toward [0ī1] or [01ī] with a first angle from [100], or toward [011] or [0ī] with a second angle from [ī00], so the upper surface of the semiconductor substrate comprises at least two lattice planes with different lattice plane directions;forming a multilayer epitaxial structure on the semiconductor substrate; andperforming surface roughening on an upper surface of the multilayer epitaxial structure on the semiconductor substrate by etching.

10. The method as claimed in claim 9, wherein the multilayer epitaxial structure comprises an n-type semiconductor layer, a p-type semiconductor layer and an active layer interposed therebetween.

11. The method as claimed in claim 9, wherein the lattice direction is defined by having a group III atom located at the [000] position of the coordinate of the unit cell as the origin.

12. The method as claimed in claim 9, wherein the first or the second angle is between 6° and 55°.

13. The method as claimed in claim 9, wherein the first or the second angle is 15°.

14. The method as claimed in claim 9, wherein the upper surfaces of the multilayer epitaxial structure and the semiconductor substrate have substantially the same surface topography.

15. The method as claimed in claim 9, wherein the roughened upper surface of the multilayer epitaxial structure has a roughening depth not less than 0.05 μm.

16. The method as claimed in claim 9, wherein the roughened upper surface of the multilayer epitaxial structure has a roughening depth between 0.05 μm and 1 μm.

17. The method as claimed in claim 9, wherein the etching comprises wet etching using HCl and H2PO4 as an etchant.

18. The method as claimed in claim 9, wherein the etching is performed for about 20 seconds.

19. The method as claimed in claim 9, wherein the etching comprises dry etching.