Referring now to the attached drawings which form a part of this original disclosure:
Selected embodiments of the present invention will now be described with reference to the drawings. It will be apparent to those skilled in the art from this disclosure that the following descriptions of the embodiments of the present invention are provided for illustration only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.
A first embodiment of the present invention will be described.
As shown in
The conductive substrate 1 is electrically conductive. The conductive substrate 1 has first and second main faces 1a and 1b. The conductive substrate 1 also has cavities 11a which are adjacent to the first main face 1a. The light emitting layer 2 emits beams of light in opposite directions which are vertical to the surfaces of the light emitting layer 2. The light emitting layer 2 emits beams of light, for example, in upward and downward directions. The light emitting layer 2 may have a multi-layered structure which, for example, includes a first cladding layer 5, a second cladding layer 6, and an activation layer 7. Further, the semiconductor light emitting device includes a passivation layer that is not illustrated.
The second electrode 4 is disposed adjacent to the second main face 11b of the conductive substrate 1. The conductive reflecting layers 11 are disposed in the cavities 11a of the conductive substrate 1. The conductive reflecting layers 11 have surfaces that are leveled to the first main face 1a of the conductive substrate 1. The buffer layer 12 is disposed adjacent to the first main face of the substrate 1 and to the conductive reflecting layers 11. The light emitting layer 2 is disposed adjacent to the buffer layer 12 so that the buffer layer 12 is interposed between the light emitting layer 2 and the conductive substrate 1. As described above, the light emitting layer 2 includes the first and second cladding layers 5 and 6, and the activation layer 7. The first cladding layer 5 is adjacent to the buffer layer 12. The activation layer 7 is adjacent to the first cladding layer 5. The second cladding layer 6 is adjacent to the activation layer 7. The activation layer 7 is interposed between the first and second cladding layers 5 and 6.
The first electrode 3 is disposed adjacent to the second cladding layer 6 so that the second cladding layer 6 is interposed between the first electrode 3 and the activation layer 7. The pad electrode 9 is disposed on the first electrode 3.
The conductive substrate 1 is electrically conductive. Atypical example of the conductive substrate 1 may include, but is not limited to, a silicon-based substrate made of silicon or silicon carbide. The conductive substrate 1 performs as a base for epitaxial growth of the buffer layer 12 and the light emitting layer 2. The conductive substrate 1 also provides a current path for the semiconductor light emitting device. The conductive substrate 1 performs as a supporter that supports the light emitting layer 2 and the first electrode 3.
The silicon-based semiconductor used for the conductive substrate 1 may have a high concentration of an impurity so that the conductive substrate 1 has a reduced resistivity. Namely, the conductive substrate 1 may be made of a highly-doped silicon based semiconductor. In some cases, the silicon-based semiconductor may contain the Group III element such as boron as a p-type impurity. The silicon-based semiconductor may, for example, have a P-type impurity concentration in the range of 5E18-5E19 [cm−3]. The silicon-based semiconductor may, for example, have a resistivity in the range of 0.0001-0.01 [Ωcm]. In other cases, the silicon-based semiconductor may contain the Group V element such as phosphorus as an N-type impurity.
The conductive substrate 1 has the first and second main faces 1a and 1b. The first main face may be (111)-face in Miller indexes. The conductive substrate 1 has a thickness in the range of 200-700 micrometers.
The conductive substrate 1 has the cavities 11a which are adjacent to the first main face 1a. The cavities 11a have walls that are curved toward the inside of the conductive substrate 1. The cavities 11a are disposed outside the first main face 1a. In plan view, the cavities 11a extend in the areas A, while the first main face 1a extends in the area D. The cavities 11a may be formed in any available set of know processes. For example, the buffer layer 12 is formed on the first main face 1a of the conductive substrate 1. The light emitting layer 2 is then formed on the buffer layer 12. The light emitting layer 2 is selectively etched to form a through-hole therein so that parts of the first main face 1a of the conductive substrate 1 are shown through the through-hole. The shown parts of the first main face 1a are then subjected to an isotropic etching process, thereby forming the cavities 11a.
The conductive reflecting layers 11 are disposed in the cavities 11a. The conductive reflecting layers 11 may be formed by filling the cavities 11a with a material that is highly reflective to the emitted light from the light emitting layer 2. The reflectivity of the material for the conductive reflecting layers 11 is higher than that of the first main face 1a of the conductive substrate 1. The material for the conductive reflecting layers 11 may be a metal or an alloy that is higher in reflectivity than the first main face 1a of the conductive substrate 1.
As shown in
As shown in
In other cases, two reflecting layers 11 are disposed, which extends opposing two of the four corners 31, 32, 33 and 34.
The conductive reflecting layers 11 are disposed in the cavities 11a. The conductive reflecting layers 11 extend in the areas A. The conductive reflecting layers 11 do not extend in the area B. Adjacent two of the four reflecting layers 11 may partially contact with each other. For example, the conductive reflecting layers 11 including the corner 31 contacts at a position 37 with the conductive reflecting layers 11 including the corner 32. The conductive reflecting layer 11 that includes the corner 32 contacts at a position 36 with the conductive reflecting layer 11 that includes the corner 33. The conductive reflecting layer 11 that includes the corner 33 contacts at a position 38 with the conductive reflecting layer 11 that includes the corner 34.
The contact position at which adjacent two of the conductive reflecting layers 11 contact with each other is not limited to the position on the side walls of the conductive substrate 1. Adjacent two of the conductive reflecting layers 11 may contact with each other at another contact position which is positioned inside the side walls of the conductive substrate 1. The contact position at which adjacent two of the conductive reflecting layers 11 contact with each other is preferably positioned outside the pad electrode 9 in plan view. If the contact position is positioned inside the pad electrode 9 in plan view, then the semiconductor light emitting device would have a reduced function of current diffusion. Thus, it would not be preferable that the contact position is positioned inside the pad electrode 9 in plan view.
As shown in
The conductive reflecting layers 11 may preferably have a resistance value that is smaller than a sheet resistance of the conductive substrate 1. In some cases, the buffer layer 12 may not be disposed. The first cladding layer 5 of the light emitting layer 2 may be made of an N-type semiconductor. In this case, the conductive reflecting layer 11 may preferably be made of a material that has a small work function. The conductive reflecting layer 11 may preferably be made of a material that includes at least any one of silver (Ag), aluminum (Al), and gold (Au).
If the first cladding layer 5 of the light emitting layer 2 may be made of an N-type semiconductor, then the conductive reflecting layer 11 may preferably be made of a material that has a large work function. The conductive reflecting layer 11 may preferably be made of a material that includes at least any one of rhodium (Rh), nickel (Ni), palladium (Pa), and platinum (Pt).
As shown in
If the conductive reflecting layers 11 have a resistance value that is higher than a sheet resistance of the conductive substrate 1, then the majority of current is likely to flow on the second current path i2 while the minority of the current is likely to flow on the first current path i1. The center area of the activation layer 7 emits strong beams of light upwardly and downwardly. The strong beam of light travels upwardly from the activation layer 7 and reaches the pad electrode 9. The upward traveling of the strong beam of light is then shielded by the pad electrode 9, thereby reducing the efficiency of light emission in the upward direction. A current blocking layer or a current confinement structure may be provided in order to prevent the reduction in the efficiency of light emission in the upward direction.
Preferably, the conductive reflecting layers 11 have a resistance value that is lower than the sheet resistance of the conductive substrate 1. Further preferably, the light emitting layer 2 has a high resistance in horizontal directions parallel to the surfaces of the light emitting layer 2. Then, the majority of current is likely to flow on the first current path i1 while the minority of the current is likely to flow on the first current path i2, whereby the non-center area of the activation layer 7 emits strong beams of light upwardly and downwardly. The upwardly-traveling strong beam of light is then emitted without being shielded by the pad electrode 9, thereby ensuring high efficiency of light emission in the upward direction. No current blocking layer or current confinement structure is needed. The downward-traveling strong beam of light is then reflected by the conductive reflecting layers 11, thereby causing an upwardly-traveling strong beam of light, or causing both upwardly-traveling and horizontally-traveling beams of light. The strong beams of light are not absorbed by the conductive substrate 1, thereby ensuring the high efficiency of light emission in the upward direction.
The wavelength of the beams of light that is emitted from the light emitting layer 2 depends on the semiconductor materials for the light emitting layer 2. The conductive material for the conductive reflecting layer 11 may be selected in light of the wavelength of the beams of light that are emitted from the light emitting layer 2 so that the downwardly-traveling beam of light having been emitted from the light emitting layer 2 is reflected by the conductive reflecting layer 11 without being absorbed into the conductive substrate 1.
The buffer layer 12 extends over the first main face 1a in the area D and the conductive reflecting layers 11 in the areas A. The buffer layer 12 may be formed by epitaxial growth. The buffer layer 12 buffers a strain that is caused by the difference in lattice constant between the conductive substrate 1 and the light emitting layer 2. The buffer layer 12 allows crystal growth of the light emitting layer 2 on the buffer layer 12. The buffer layer 12 may have a multi-layered structure. For example, the buffer layer 12 has seven layers, wherein the multiplayer structure of the buffer layer 12 has alternating stacks of first and second buffer layers. Namely, the first and second buffer layers are alternately stacked six times and further the first buffer layer is stacked on the top second buffer layer, thereby forming the multilayered structure of the buffer layer 12. The buffer layer 12 includes four of first buffer layer and three of the second buffer layer.
The first buffer layer may be made of AlcMdGa1-c−dN where 0≦c≦1, 0≦d≦1, 0≦c+d≦1, M is indium (In) or boron (B). The first buffer layer may preferably be made of AlN. The thickness of the first buffer layer may be in the range of 0.2 nm-20 nm, and preferably in the range of 1 nm-5 nm which may cause tunneling effect.
The second buffer layer may be made of AleMfGa1-e−fN where 0≦e≦c≦1, 0≦f≦1, 0≦e+f≦1, M is indium (In) or boron (B). The second buffer layer does not contain aluminum or does contain aluminum but at a lower compositional ratio than that of the first buffer layer. The first buffer layer may preferably be made of GaN. The thickness of the second buffer layer may be 5-50 times as large as that of the first buffer layer. Preferably, the thickness of the second buffer layer may be 10-40 times as large as that of the first buffer layer.
The light emitting layer 2 may be made of Group III-V compound semiconductors. The light emitting layer 2 has a double hetero structure that consists of the first cladding layer 5 of a first conductivity type, the second cladding layer 6 of a second conductivity type, and the activation layer 7 that is interposed between the first and second cladding layers 5 and 6.
The first cladding layer 5 may be made of a Group III-V compound semiconductor that is doped with an N-type impurity. For example, the first cladding layer 5 may be made of N-doped AlaMbGa1-a−bN where 0≦a≦1, 0≦b≦1, 0≦a+b≦1, M is indium (In) or boron (B). Preferably, the first cladding layer 5 may be made of a nitride compound semiconductor such as gallium nitride (GaN). Preferably, the first cladding layer 5 may have a thickness of approximately 500 nm.
The activation layer 7 may be made of a Group III-V compound semiconductor free of any impurity. For example, the activation layer 7 may be made of AlXMYGa1-X−YN where 0≦X<1, 0≦Y<1, 0≦X+Y<1, M is indium (In) or boron (B).
The second cladding layer 6 may be made of a Group III-V compound semiconductor that is doped with a P-type impurity. For example, the first cladding layer 5 may be made of P-doped AlXMYGa1-X−YN where 0≦X<1, 0≦Y<1, 0≦X+Y<1, M is indium (In) or boron (B). Preferably, the second cladding layer 6 may be made of a nitride compound semiconductor such as gallium nitride (GaN).
The semiconductor light emitting device needs to have the p-n junction. Thus, the light emitting layer 2 needs to have the p-n junction. The light emitting layer 2 may be modified as long as the light emitting layer 2 has the p-n junction. In some cases, the light emitting layer 2 may be modified to be free of the activation layer 7. In other cases, the light emitting layer 2 may also be modified to include, instead of the activation layer 7, a single quantum well structure that causes tunneling effect. In other cases, the light emitting layer 2 may also be modified to include, instead of the activation layer 7, a multiple quantum well structure that causes tunneling effect.
In some cases, the semiconductor light emitting device may be modified not to include the buffer layer 12, wherein the first cladding layer 5 of N-type conductivity is adjacent to the conductive substrate 1 of P-type conductivity. The interface between the N-type first cladding layer 5 and the P-type substrate 1 forms the hetero junction and an alloyed region. These reduce the voltage drop that appears on the interface between the N-type first cladding layer 5 and the P-type substrate 1 when the semiconductor light emitting device is forward-biased.
In accordance with the above descriptions, the buffer layer 12 is discriminated from the double hetero structure that forms the light emitting layer 2. It is possible that a multi-layered structure that includes at least a structure that emits light would be so called to as a light emitting layer. For example, a light emitting layer might include not only the above-described light emitting layer 2 but also the buffer layer 12.
The first electrode 3 is disposed on the main face of the light emitting layer 2. The first electrode 3 is electrically conductive to the light emitting layer 2. Namely, the first electrode 3 is disposed on the main face of the second cladding layer 6. The first electrode 3 is electrically conductive to the second cladding layer 6. The first electrode 3 may be made of a transparent material so as to allow that the beam of light from the light emitting layer 2 travels through the first electrode 3. The first electrode 3 may have an ohmic contact with the light emitting layer 2. The first electrode 3 may be made of indium tin oxide (ITO). Indium oxide (In2O3) is mixed with tin oxide (SnO2) at about a few percents to prepare indium tin oxide (ITO). The thickness of the first electrode 3 may be about 100 nm.
When the second cladding layer 6 is made of a P-type semiconductor, the first electrode 3 may be made of a metal selected from nickel (Ni), platinum (Pt), palladium (Pd), rhodium (Rh), and gold (Al), or an alloy that contains at least one of those metals. When the second cladding layer 6 is made of an N-type semiconductor, the first electrode 3 may be made of a metal selected from aluminum (Al), titanium (Ti), and gold (Al), or an alloy that contains at least one of those metals.
The pad electrode 9 is disposed on a center area of the first electrode 3. The pad electrode 9 allows an electrical connection to an external device. The pad electrode 9 may be made of gold (Au) or aluminum (Al). The pad electrode 9 is disposed not to cover the entirety of the first electrode 3. In plan view, the first electrode 3 has a first portion that is covered by the pad electrode 9 and a second portion that is shown. The second portion surrounds the first portion. The pad electrode 9 is adapted to carry out wire-bonding process. The thickness of the pad electrode 9 is sufficient to carry out wire-bonding process. For example, the thickness of the pad electrode 9 may be in the range from 100 nm to 100 μm. The pad electrode 9 has almost no transparency to light that has been emitted from the light emitting layer 2. The pad electrode 9 that is bonded with a connection wire has no transparency to light that has been emitted from the light emitting layer 2.
The second electrode 4 is disposed on the second main face 1b of the conductive substrate 1. The second electrode 4 may cover the entirety of the second main face 1b of the conductive substrate 1. The second electrode 4 may be formed on the second main face 1b of the conductive substrate 1 by vacuum evaporation. In some cases, gold (Au) can be deposited on the second main face 1b of the conductive substrate 1 to form the second electrode 4 of gold (Au). In other cases, gold (Au) and germanium (Ga) can be deposited on the second main face 1b of the conductive substrate 1, thereby forming the second electrode 4 of gold (Au) and germanium (Ga). In other cases, gold (Au), germanium (Ga) and nickel (Ni) can be deposited on the second main face 1b of the conductive substrate 1, thereby forming the second electrode 4 of gold (Au), germanium (Ga) and nickel (Ni). The second electrode 4 is electrically and physically connected with the conductive substrate 1.
In some cases, the semiconductor light emitting device can be modified to further include, instead of the second cladding layer 6, a current diffusion layer that is interposed between the activation layer 7 and the first electrode 3. The current diffusion layer may be a known current diffusion layer. In other cases, the semiconductor light emitting device can be modified to further include, instead of the second cladding layer 6, a contact layer that is interposed between the activation layer 7 and the first electrode 3. The contact layer may be a known contact layer. In other cases, the semiconductor light emitting device can be modified to further include a current diffusion layer that is interposed between the activation layer 7 and the first electrode 3, wherein the current diffusion layer is surrounded by the second cladding layer 6, provided that the current diffusion layer is positioned below but in plan view it does not extend beyond the pad electrode 9. In other cases, it is possible to reverse the conductivity type of each of the conductive substrate 1, the first cladding layer 5, the activation layer 7 and the second cladding layer 6.
The shape of each element for the semiconductor light emitting device is optional. For example, the shape in plan view of the pad electrode 9 may be circle, rectangle and other polygonal. The shape in plan view of each of the conductive substrate 1 and the light emitting layer 2 is also optional. The shape in plan view may be rectangle or other polygonal or circle.
With reference to
The first cladding layer 5 is formed on the buffer layer 12 by the known metal organic chemical vapor deposition method (MOCVD). The activation layer 7 is then formed on the first cladding layer 5 by the known metal organic chemical vapor deposition method (MOCVD). The second cladding layer 6 is then formed on the activation layer 7 by the known metal organic chemical vapor deposition method (MOCVD). The stack of the first cladding layer 5, the activation layer 7 and the second cladding layer 6 provides the double hetero structure which forms the light emitting layer 2.
The first electrode 3 is formed on the second cladding layer 6 by any available method such as a vacuum evaporation method, a sputtering method and a chemical vapor deposition method. Indium tin oxide is deposited on the second cladding layer 6 to form the first electrode 3 of indium tin oxide on the second cladding layer 6. The first electrode 3 of indium tin oxide has a low resistive contact such as ohmic contact with the second cladding layer 6. The conductive substrate 1 can then be annealed. It is also possible to carry out an anneal process after an evaporation of a metal film for the pad electrode 9 has been carried out.
With reference to
With reference to
With reference to
With reference to
With reference to
With reference to
With reference to
If the side edges of the conductive substrate 1 and the conductive reflecting layers 11 are positioned in plan view outside the edge edges of the light emitting layer 2, the side edges of the conductive substrate 1 and the conductive reflecting layers 11 are etched so that the side edges of the conductive substrate 1 and the conductive reflecting layers 11 are aligned in plan view to the edge edges of the light emitting layer 2, thereby completing the semiconductor light emitting device of
In accordance with the above-described embodiments, the semiconductor light emitting device can be formed so that the conductive reflecting layers are formed without carrying out any process for combining a substrate with a layered structure. If the semiconductor light emitting device is formed through the process for combining the substrate with the layered structure, then the luminance property of the device may depend on the adhesiveness between the substrate and the layered structure. If the semiconductor light emitting device is formed without carrying out the process for combining the substrate with the layered structure, then the luminance property of the device can be ensured and there is no problem with the adhesiveness between the substrate and the layered structure.
It is assumed that the epitaxial growth processes are carried out after the reflecting layers 11 are formed. Namely, the light emitting layer 2 is epitaxially grown over the reflecting layers 11. In this case, however, it is not easy to obtain high crystal quality of the light emitting layer 2 over the reflecting layers 11. The luminance property of the light emitting layer 2 depends on the crystal quality of the light emitting layer 2. The light emitting layer 2 over the reflecting layers 11 is unlikely to have desired luminance properties.
In accordance with this embodiment, the conductive reflecting layers 11 are formed after the light emitting layer 2 is epitaxially grown over the conductive substrate 1. It is easy to obtain good crystal quality of the light emitting layer 2. There is an increased flexibility to select a material for the conductive reflecting layers 11 that have low resistive contacts with the light emitting layer and that reflect light that have been emitted from the light emitting layer.
The beam of light that has emitted from the light emitting layer 2 is partially reflected by the conductive reflecting layers 11 and partially transmitted through the conductive reflecting layers 11. The transmitted part of the beam of light reaches the reflecting layers 13 and reflected by the reflecting layers 13. The reflecting layers 13 that are disposed in the conductive reflecting layers 11 increases the efficiency of emission of light from the semiconductor light emitting device.
The conductive reflecting layers 11 and the reflecting layers 13 can be formed as follows. A material for the conductive reflecting layers 11 is deposited on the walls of the cavities 11a so that the conductive reflecting layers 11 having smaller cavities are formed in the cavities 11. Another material for the reflecting layers 13 is deposited to fill up the smaller cavities.
A second embodiment of the present invention will be described.
The semiconductor light emitting device of
The semiconductor light emitting device of
The semiconductor light emitting device of
The irregular interfaces between the semiconductor light emitting layer 2 and the conductive reflecting layers 11 cause irregular reflection of the beam of light that has been emitted from the light emitting layer 2. Irregular reflection by the irregular interfaces leads to the increased reflection of the beam of light, thereby increasing the efficiency of the emission of the beam of light from the semiconductor light emitting device.
The above-described processes of
An etchant is prepared, which contains a phosphoric acid (H3PO4) or a potassium hydroxide (KOH). The etchant is heated to about 70° C., thereby preparing a hot etchant. As described above, the oxide film 42 is made of SiO2. The buffer layer 12 is made of the Group III-V compound semiconductor. The semiconductor light emitting layer 2 is also made of the Group III-V compound semiconductor. The etching rate of SiO2 of the oxide film 42 is lower than the etching rate of the Group III-V compound semiconductor of the buffer layer 12 or the semiconductor light emitting layer 2. The buffer layer 12 is partially exposed to the cavities 11a as shown in
If the semiconductor light emitting device is modified not to include the buffer layer 12, the semiconductor light emitting layer 2 is partially exposed to the cavities 11a. The substrate 1 is exposed to the hot etchant, so that the exposed surfaces of the semiconductor light emitting layer 2 are etched by the etchant thereby forming irregular surfaces, while the oxide film 42 is not etched by the etchant. The irregular surfaces of the semiconductor light emitting layer 2 face to the cavities 11a.
With reference to
With reference to
With reference to
If the side edges of the conductive substrate 1 and the conductive reflecting layers 11 are positioned in plan view outside the edge edges of the light emitting layer 2, the side edges of the conductive substrate 1 and the conductive reflecting layers 11 are etched so that the side edges of the conductive substrate 1 and the conductive reflecting layers 11 are aligned in plan view to the edge edges of the light emitting layer 2, thereby completing the semiconductor light emitting device of
In accordance with this embodiment, the semiconductor light emitting device of
The irregular interfaces between the semiconductor light emitting layer 2 and the conductive reflecting layers 11 cause irregular reflection of the beam of light that has been emitted from the light emitting layer 2. Irregular reflection by the irregular interfaces leads to the increased reflection of the beam of light, thereby increasing the efficiency of the emission of the beam of light from the semiconductor light emitting device.
The beam of light that has emitted from the light emitting layer 2 is partially reflected by the conductive reflecting layers 11 and partially transmitted through the conductive reflecting layers 11. The transmitted part of the beam of light reaches the reflecting layers 13 and reflected by the reflecting layers 13. The reflecting layers 13 that are disposed in the conductive reflecting layers 11 increases the efficiency of emission of light from the semiconductor light emitting device.
The conductive reflecting layers 11 and the reflecting layers 13 can be formed as follows. A material for the conductive reflecting layers 11 is deposited on the walls of the cavities 11a so that the conductive reflecting layers 11 having smaller cavities are formed in the cavities 11. Another material for the reflecting layers 13 is deposited to fill up the smaller cavities.
The other modified semiconductor light emitting device of
The light emitting layer 2 emits the beam of light, a part of which travels toward the outside portions of the conductive reflecting layers 11 as shown by an arrow mark 51 in
No etching process needs to be carried out after the dicing process has been carried out.
It is also possible as a modification that the other modified semiconductor light emitting device of
The beam of light that has emitted from the light emitting layer 2 is partially reflected by the conductive reflecting layers 11 and partially transmitted through the conductive reflecting layers 11. The transmitted part of the beam of light reaches the reflecting layers 13 and reflected by the reflecting layers 13. The reflecting layers 13 that are disposed in the conductive reflecting layers 11 increases the efficiency of emission of light from the semiconductor light emitting device.
The conductive reflecting layers 11 and the reflecting layers 13 can be formed as follows. A material for the conductive reflecting layers 11 is deposited on the walls of the cavities 11a so that the conductive reflecting layers 11 having smaller cavities are formed in the cavities 11. Another material for the reflecting layers 13 is deposited to fill up the smaller cavities.
A third embodiment of the present invention will be described.
The vacant cavities 11a have cavity walls which are separated from the film-shaped conductive reflecting layers 11 shown in
The conductive substrate 1 of
The semiconductor light emitting device can also be modified not to include the buffer layer 12. In this case, the conductive substrate 1 has a mechanical contact area with the light emitting layer 2, where the mechanical contact area means an area through which a mechanical stress is transmitted between the conductive substrate 1 and the light emitting layer 2. The mechanical contact area of the conductive substrate 1 corresponds to a physical contact area between the substrate 1 and the light emitting layer 2. The mechanical stress is caused by the difference in linear expansion coefficient between the light emitting layer 2 and the conductive substrate 1. Thus, the vacant cavities 11a reduce the mechanical contact area, thereby reducing the mechanical stress between the conductive substrate 1 and the light emitting layer 2.
The film-shaped conductive reflecting layers 11 have the edges that are aligned in plan view to the edges of the conductive substrate 1. The light emitting layer 2 has the edges that are aligned in plan view to the edges of the buffer layer 12. The aligned edges of the light emitting layer 2 and the buffer layer 12 are positioned in plan view inside the aligned edges of the film-shaped conductive reflecting layers 11 and the conductive substrate 1. In other words, the edges of the film-shaped conductive reflecting layers 11 are positioned in plan view outside the edges of the light emitting layer 2. The film-shaped conductive reflecting layers 11 have outside and inside portions, wherein the outside portions are positioned in plan view outside the light emitting layer 2, and the inside portions are overlapped in plan view by the light emitting layer 2.
The light emitting layer 2 emits the beam of light, a part of which travels toward the outside portions of the film-shaped conductive reflecting layers 11 as shown by an arrow mark 53 in
The semiconductor light emitting device of
The above-described processes of
With reference to
Metals such as silver are highly adhesive on metals. Metals such as silver are adhesive on compound semiconductors. Metals such as silver are poorly adhesive on silicon. Metals such as silver are not adhesive on silicon dioxide. Namely, the electrolytic plating process is carried out under conditions such that silver is deposited on the compound semiconductor, while silver is not adhered on silicon and silicon oxide. The buffer layer 12 is made of a compound semiconductor. The semiconductor light emitting layer 2 is made of compound semiconductors. The conductive substrate 1 is made of silicon. Thus, silver is deposited only the bottom surface of the outside portion of the buffer layer 12, while no deposition of silver appears on the cavity wall 11a of the conductive substrate 1 and on the silicon oxide film 42. The film-shaped conductive reflecting layers 11 extend under the outside portion of the buffer layer 12 and over the cavities 11a.
With reference to
With reference to
In accordance with this embodiment, the semiconductor light emitting device of
The electrolytic plating process is carried out under conditions such that silver is deposited on the compound semiconductor, while silver is not adhered on silicon and silicon oxide. The semiconductor light emitting layer 2 is made of a compound semiconductor. The conductive substrate 1 is made of silicon. Thus, silver is deposited only the bottom surface of the outside portion of the semiconductor light emitting layer 2, while no deposition of silver appears on the cavity wall 11a of the conductive substrate 1 and on the silicon oxide film 42. The film-shaped conductive reflecting layers 11 extend under the outside portion of the semiconductor light emitting layer 2 and over the cavities 11a.
A fourth embodiment of the present invention will be described. The fourth embodiment provides a composite semiconductor device that includes a combination of the semiconductor light emitting device with a protective device that protects the semiconductor light emitting device. The light emitting device including the light emitting layer of compound semiconductors may often have low electrostatic discharge voltage. For example, application of a high surge voltage over 100V to the semiconductor light emitting device may break the semiconductor light emitting device. For the purpose of electrostatic discharge protection, the protective device and the semiconductor light emitting device may be mounted together on the same package. The protective device is designed to protect the semiconductor light emitting device. The protective device may be realized by at least a diodes or at least a capacitor.
The semiconductor light emitting device may include the first region 8 of the conductive substrate 1, the buffer layer 12, the semiconductor light emitting layer 2, the conductive reflecting layer 11, a light-transparent conductive film 19, and the first and second electrodes 3 and 4. The protective device may include the second region 24 of the conductive substrate 1, a Schottky contact metal layer 18, and the first and second electrodes 3 and 4. The stack of the buffer layer 12 and the semiconductor light emitting layer 2 forms a compound semiconductor light epitaxial layer.
In some cases, the conductive substrate 1 may be a p-type single crystal silicon substrate that contains a p-type impurity. The p-type impurity may be a Group III element such as boron (B). The conductive substrate 1 may have first and second main faces 1a and 1b opposing each other. The conductive substrate 1 has the first and second regions for the semiconductor light emitting device and the protective device, respectively. The second region 24 is positioned at the center of the conductive substrate 1, while the first region 8 surrounds the second region 24.
In some cases, the conductive substrate 1 may have a p-type impurity concentration in the range of approximately 5E18 [cm−3] to approximately 5E19 [cm−3]. The conductive substrate 1 may have a resistivity in the range of approximately 0.0001 [Ωcm] to approximately 0.01 [Ωcm]. The conductive substrate 1 may provide a current path for the semiconductor light emitting device and the protective device. Namely, the second region 24 of the conductive substrate 1 performs as a body of the Schottky barrier diode, wherein the body provides a current path for the Schottky barrier diode. The first region 8 of the conductive substrate 1 surrounds the second region 24. The first region 8 of the conductive substrate 1 provides a current path for the light emitting diode. The conductive substrate 1 further performs as a substrate for epitaxial growth of the buffer layer 12 and the semiconductor light emitting layer 2. The conductive substrate 1 mechanically supports the semiconductor light emitting layer 2 and the first electrode 3.
In some cases, the conductive substrate 1 has the first main face 1a which may include a center recess 25, a side recess, and a flat portion which separates the center recess 25 from the side recess. The center recess 25 is positioned at the center of the first main face 1a of the conductive substrate 1. In plan view, the flat portion surrounds the center recess 25. In plan view, the side recess surrounds the flat portion. The side recess defines the periphery edge of the first main face 1a of the conductive substrate 1.
In other cases, the conductive substrate 1 can be modified to have a modified main face 1a that is flat entirely.
In other cases, it is possible as a modification that the conductivity type of the conductive substrate 1 is an n-type.
In other cases, the conductive substrate 1 can be modified such that the first region 8 for the light emitting device is higher in impurity concentration than the second region 24 for the protective device. In this case, the first region 8 is lower in resistivity than the second region 24. Reducing the resistivity of the first region 8 can reduce the voltage drop that appears in the first region 8 when the light emitting device is operated.
The compound semiconductor epitaxial layer includes the buffer layer 12 and the light emitting layer 2. In other words, the compound semiconductor epitaxial layer has a multi-layered hetero structure that includes plural Group III-V compound semiconductor layers. The light emitting layer 2 includes the first cladding layer 5, the activation layer 7, and the second cladding layer 6. The compound semiconductor epitaxial layer has a center hole 16 which penetrates through the compound semiconductor epitaxial layer. Namely, the center hole 16 penetrates through the stack of the light emitting layer 2 and the buffer layer 12. The compound semiconductor epitaxial layer has an upper surface that is an upper main face 2a of the light emitting layer 2. The compound semiconductor epitaxial layer has a lower surface that is a lower main face 12a of the buffer layer 12. The center hole 16 communicates with the center recess 25 of the conductive substrate 1.
The center hole 16 and the center recess 25 may be formed by selectively etching the compound semiconductor epitaxial layer and the conductive substrate 1, after the compound semiconductor epitaxial layer is epitaxially grown on the main face 1a of the conductive substrate 1. If the conductive substrate is made of silicon, then the center recess has side and bottom walls of silicon. The center hole 16 and the center recess 25 forms a combined hole. The combined hole has a tapered side wall so that the combined hole is tapered in the direction of depth. Namely, the combined hole decreases in horizontally sectioned area as the depth thereof increases. The combined hole is positioned over the second region 24 of the conductive substrate 1. An insulating layer 17 is formed on the tapered side wall of the combined hole that includes the center hole 16 and the center recess 25.
The first electrode 3 includes a transparent conductive film 19 as a first part and a bonding pad 20 as a second part. The bonding pad 20 is electrically connected to the transparent conductive film 19. A Schottky metal layer 18 is disposed between the bonding pad 20 and the second region 24 of the conductive substrate 1. The Schottky metal layer 18 is disposed on the bottom wall of the combined hole, namely on the top surface of the second region 24 of the conductive substrate 1. The Schottky metal layer 18 is disposed in contact with the top surface of the second region 24 of the conductive substrate 1. The bonding pad 20 is also disposed in contact with the Schottky metal layer 18. The bonding pad 20 provides an electrical connection between the transparent conductive film 19 and the Schottky metal layer 18. The bonding pad 20 also provides another electrical connection to an external element.
The bonding pad 20 has a tapered portion which is in the center hole 16 which has the side wall covered by the insulating film 17. The bonding pad 20 also has a side portion which is positioned over the inside portion of the stack of the transparent conductive film 19 and the light emitting layer 2. The bonding pad 20 is electrically connected via the transparent conductive film 19 to the light emitting layer 2.
It is possible as a modification that the transparent conductive film 19 is not provided so that the side portion of the bonding pad 20 ohmically contacts with the light emitting layer 2. In the absence of the transparent conductive film 19, the side portion of the bonding pad 20 may, if necessary, ohmically contact with the main face 2a of the light emitting layer 2 so as to allow a current flow from the first electrode 3 to the light emitting layer 2. In the absence of the transparent conductive film 19, the side portion of the bonding pad 20 performs as the first part which is eclectically connected with the light emitting layer 2.
The transparent conductive film 19 may allow that a current is uniformly applied to the entire region of the light emitting layer 2. Namely, the transparent conductive film 19 is useful to uniformly apply the current to the entire region of the light emitting layer 2. Actually, however, it is not easy to realize 100% optical transmittance of the transparent conductive film 19. The transparent conductive film 19 with an optical transmittance less than 100% absorbs light. The transparent conductive film 19 with an optical transmittance less than 100% necessarily decreases emission efficiency. In addition, the transparent conductive film 19 necessarily increases the cost of the semiconductor light emitting device. It may be possible to consider whether the transparent conductive film 19 should be provided or not, in light of the emission efficiency and the cost.
The transparent conductive film 19 performs as the first part of the first electrode 3. The transparent conductive film 19 is disposed on the main face 2a of the light emitting layer 2, so that the transparent conductive film 19 ohmically contacts with the main face 2a of the light emitting layer 2. The surface of the second cladding layer 6 constitutes the main face 2a of the light emitting layer 2. In other words, the transparent conductive film 19 is disposed on the second cladding layer 6, so that the transparent conductive film 19 ohmically contacts with the second cladding layer 6. The transparent conductive film 19 allows the current to be uniformly applied to the entire region of the light emitting layer 2. The transparent conductive film 19 allows light as emitted from the light emitting layer 2 to be propagated through the transparent conductive film 19 and emitted from the semiconductor light emitting device.
In some cases, the transparent conductive film 19 may be realized by an indium tin oxide film (ITO film) having a thickness of approximately 100 nm. In other cases, the transparent conductive film 19 may be realized by another metal film that contains any one or mixture of nickel (Ni), platinum (Pt), palladium (Pd), rhodium (Ro), ruthenium (Ru), osmium (Os), iridium (Ir), and gold (Au).
The Schottky metal layer 18 performs as the Schottky electrode. The Schottky metal layer 18 is disposed on the bottom of the combined hole. The insulating layer 17 has a center opening 17a which is positioned over the top surface of the second region 24 of the conductive substrate 1. In the center opening 19a, the Schottky metal layer 18 contacts with the top surface of the second region 24 of the conductive substrate 1. Namely, in the center opening 19a, the Schottky metal layer 18 has Schottky junction with the second region 24 of the conductive substrate 1. In some cases, the Schottky metal layer 18 may be made of one of titanium (Ti), platinum (Pt), chromium (Cr), aluminum (Al), samarium (Sm), platinum silicide (PtSi), and palladium silicide (Pa2Si). The combination of the Schottky metal layer 18 and the second region 24 of the conductive substrate 1 constitutes the Schottky barrier diode that performs as the protective device.
The bonding pad 20 performs as the second part of the first electrode 3. The bonding pad 20 as the second part of the first electrode 3 is positioned in plan view inside the transparent conductive film 19 as the first part of the first electrode 3. The bonding pad 20 is smaller in plan area than the light emitting layer 2. The bonding pad 20 may be made of a metal that allows a bonding wire 26 to be bonded to the bonding pad 20. The bonding wire 26 may be made of aluminum (Al) or gold (Au). The bonding pad 20 contacts with the Schottky metal layer 18. The bonding pad 20 also contacts with the transparent conductive film 19. Namely, the bonding pad 20 is electrically connected between the transparent conductive film 19 and the Schottky metal layer 18. A passivation film 27 is provided which covers the top surface and outside sloped wall of the stack of the transparent conductive film 19 and the light emitting layer 2. The passivation film 27 has an opening 27a in which the bonding pad 20 contacts with the transparent conductive film 19. In the combined hole, the bonding pad 20 contacts with the Schottky metal layer 18.
In plan view, the bonding pad 20 does overlap the light emitting layer 2 partially but not entirely. Namely, in plan view, the bonding pad 20 does not overlap at least partially the light emitting layer 2. Further, in plan view, the bonding pad 20 does at least partially overlap the protective device. Further, the bonding pad 20 provides an electrical connection between the transparent conductive film 19 as the first part of the first electrode 3 and the Schottky metal layer 18 as the Schottky electrode.
As shown in
The bonding pad 20 has a thickness which is sufficiently thick for allowing the bonding wire 26 to be bonded to the bonding pad 20. Typically, the thickness of the bonding pad 20 may be, but is not limited to, in the range of 100 nm to 100 μm. In other words, the bonding pad 20 may be so thick as to prevent light from transmitting through it. Further, the combination of the bonding pad 20 with the bonding wire 26 is so thick as to prevent light from transmitting through it. The insulating film 17 is provided to insulate between the bonding pad 20 and the light emitting layer 2. In some cases, the insulating film 17 and the passivation film 27 may be formed in the same processes.
As shown in
The second electrode 4 may be disposed entirely on the second main face 1b of the conductive substrate 1. Namely, the second electrode 4 contacts with both the first and second regions 8 and 24 of the conductive substrate 1. The second electrode 4 may be made of a metal. The second electrode 4 may ohmically contacts with both the first and second regions 8 and 24 of the conductive substrate 1.
In other cases, it is possible as a modification that the second electrode 4, as represented by a broken line in
The bonding pad 20 of the first electrode 3 may provide external connection to any external element or device through the bonding wire 26. The bonding pad 20 may also provide electrical interconnection between the light emitting device and the protective device. The bonding pad 20 interconnects the Schottky metal layer 18 as the Schottky electrode of the Schottky barrier diode and the transparent conductive film 19 as the electrode of the light emitting device. The second electrode 4 performs as a common electrode for both the Schottky barrier diode and the light emitting device.
The Schottky barrier diode 62 becomes conductive upon application of a reverse over-voltage to the light emitting diode 61. A typical example of the reverse over-voltage is a serge voltage. The light emitting diode 61 receives the voltage that is limited by the forward voltage of the Schottky barrier diode 62. The Schottky barrier diode 62 protects the light emitting diode 61 from the reverse over-voltage such as a serge voltage.
The Schottky barrier diode 62 has a starting voltage in forward direction that makes the Schottky barrier diode 62 conductive. The forward voltage is set lower than the maximum reverse voltage of the light emitting diode 61. The starting voltage in forward direction of the Schottky barrier diode 62 is set lower than a voltage that may break the light emitting diode 61. Preferably, the starting voltage in forward direction of the Schottky barrier diode 62 may be higher than the reverse-biased voltage that is applied to the light emitting diode 61 in normal operation mode and lower than the voltage that may break the light emitting diode 61.
As described above with reference to
It is possible as a modification that the cavity 11a extends under the outside portion of the stacked structure of the buffer layer 12 and the light emitting layer 2. Thus, the conductive reflecting layer 11 in the cavity 11a also extend under the outside portion of the stacked structure of the buffer layer 12 and the light emitting layer 2. Namely, it is possible as a modification that the conductive reflecting layer 11 has the outside edge that is positioned in plan view inside the outside edge of the light emitting layer 2 or is aligned to the outside edge of the light emitting layer 2.
The conductive reflecting layer 11 has an inside portion which contacts with the bottom surface of the outside portion of the stacked structure of the buffer layer 12 and the light emitting layer 2. In some cases, the conductive reflecting layer 11 may have a smooth interface with the outside portion of the stacked structure of the buffer layer 12 and the light emitting layer 2. In other cases, the conductive reflecting layer 11 may have an irregular interface with the outside portion of the stacked structure of the buffer layer 12 and the light emitting layer 2.
It is also possible as a modification that the light emitting layer 2 contacts with the first main face 1a and the inside portion of the conductive reflecting layer 11, in the absence of the buffer layer 12. In some cases, the conductive reflecting layer 11 may have a smooth interface with the outside portion of the light emitting layer 2. In other cases, the conductive reflecting layer 11 may have an irregular interface with the outside portion of the light emitting layer 2. The irregular interface may be as described with reference to
It is also possible as a further modification that the conductive reflecting layer 11 is film-shaped as described with reference to
It is also possible as a still further modification that the conductive reflecting layer 11 is film-shaped as described with reference to
The second region 24 of the conductive substrate 1 is present for the protective device. The second region 24 of the conductive substrate 1 is positioned under the bonding pad 20. This may avoid the reduction of the light-emitting area of the light emitting device. This may permit the size reduction of the composite semiconductor device. Further, the conductive reflecting layer 11 has the outside portion that is positioned in plan view outside the light emitting layer 2.
The light emitting layer 2 emits the beam of light, a part of which travels toward the outside portions of the conductive reflecting layers 11. The partial beam of light is then reflected by the upper surface of the outside portion of the conductive reflecting layer 11. The reflected beam of light travels upwardly, thereby improving the efficiency of the emission of light.
Each of the bonding pad 20 and the second electrode 4 provides interconnections between the light emitting diode 61 and the Schottky barrier diode 62 and also permit an external connection to any external element or device. This configuration can simplify the structure of the composite semiconductor device, thereby reducing the size and the manufacturing cost of the composite semiconductor device. The second region 24 for forming the protective device is provided in the conductive substrate 1. This configuration reduces the manufacturing cost of the Schottky barrier diode as the protective device.
If the light emitting layer 2 has a high horizontal resistance, the presence of the transparent conductive film 19 causes the majority of current to flow through the outside portion of the first region 8 of the conductive substrate 1. In this case, the conductive reflecting layers 11 may have a current path of the majority of current. The reduction in the resistance of the current path of the conductive reflecting layers 11 causes the majority of current to flow through the current path of the conductive reflecting layers 11. Namely, the reduction in the resistance of the current path of the conductive reflecting layers 11 causes the majority of current to flow through the outside portion of the first region 8 of the conductive substrate 1. The majority of current being injected into the outside portion of the light emitting layer 2 causes the outside portion of the light emitting layer 2 to emit strong beam of light, thereby improving the light emitting efficiency. Namely, the composite semiconductor device can be regarded to have a function of current diffusion to the outside portion.
The n-type semiconductor region 28 may be formed by a selective ion implantation, wherein an n-type impurity is implanted and diffused into the conductive substrate 1 of p-type. The n-type semiconductor region 28 has a p-n junction with the conductive substrate 1 of p-type. Namely, the n-type semiconductor region 28 has a top surface which faces to the center recess 25. The n-type semiconductor region 28 may have an ohmic contact with the bonding pad 20. The n-type semiconductor region 28 has the outside edge that is positioned in plan view inside the outside edge of the bonding pad 20. The first modified composite semiconductor device of
The conductive substrate 1 also has the two-dimensional periodical array of the cavities 11a. The cavities 11a are positioned under the penetrating holes and these adjacent portions of the stacked structure which are adjacent to the penetrating holes. The conductive substrate 1 also has the two-dimensional periodical array of the conductive reflecting layers 11 that fill up the cavities 11a. The conductive reflecting layers 11 are positioned under the penetrating holes and these adjacent portions of the stacked structure which are adjacent to the penetrating holes. The conductive reflecting layers 11 contact with the adjacent portions of the stacked structure which are adjacent to the penetrating holes. Each of the penetrating holes is covered by an insulating film 29, thereby forming a closed hollow which is defined by the cavity wall and the insulating film 29.
An n-type semiconductor region 28 is selectively provided in the second region 24 of p-type of the conductive substrate 1. The n-type semiconductor region 28 is adjacent to the first main face 1a of the conductive substrate 1. The n-type semiconductor region 28 has a p-n junction with the second region 24 of p-type of the conductive substrate 1. The second modified composite semiconductor device of
The first and second modified complex semiconductor devices of
It is also possible as a further modification that the light emitting layer 2 contacts with the first main face 1a and the inside portion of the conductive reflecting layer 11, in the absence of the buffer layer 12. In some cases, the conductive reflecting layer 11 may have a smooth interface with the penetrating-hole-adjacent portion of the light emitting layer 2. In other cases, the conductive reflecting layer 11 may have an irregular interface with the outside portion of the light emitting layer 2. The irregular interface may be as described with reference to
It is also possible as a further modification that the conductive reflecting layer 11 is film-shaped as described with reference to
It is also possible as a still further modification that the conductive reflecting layer 11 is film-shaped as described with reference to
It is also possible as yet a further modification that the Schottky metal layer is provided instead of the n-type semiconductor region 28.
While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description, and is only limited by the scope of the appended claims.
Number | Date | Country | Kind |
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2006-229404 | Aug 2006 | JP | national |