This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2012-168940, filed on Jul. 30, 2012; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor light emitting device.
It is desirable to increase the luminous efficiency of semiconductor light emitting devices such as LDs (Laser Diodes), LEDs (Light Emitting Diodes), etc. For example, the radiative combination efficiency of the active layer of such a semiconductor light emitting device decreases when the injection of holes into the active layer is insufficient.
According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting layer, a first intermediate layer, and a second intermediate layer. The n-type semiconductor layer includes a nitride semiconductor. The p-type semiconductor layer includes a nitride semiconductor provided on a [0001]-direction side of the n-type semiconductor layer. The light emitting layer is provided between the n-type semiconductor layer and the p-type semiconductor layer. The light emitting layer includes a plurality of barrier layers of AlxbInybGa1-xb-ybN (0≦xb≦1 and 0≦yb≦1) and a well layer of AlxwInywGa1-xw-ywN (0≦xw≦1, xw≦xb, 0<yw≦1, and yb<yw) provided between the plurality of barrier layers. A bandgap energy of the well layer is less than a bandgap energy of the plurality of barrier layers. The first intermediate layer is provided between the light emitting layer and the p-type semiconductor layer. The first intermediate layer includes AlxaInyaGa1-xa-yaN (0<xa≦1, xb≦xa, 0<ya≦1, and ya<yw). A bandgap energy of the first intermediate layer is greater than the bandgap energy of the barrier layers. The second intermediate layer includes a first portion and a second portion. The first portion is in contact with a p-side barrier layer of the plurality of barrier layers most proximal to the p-type semiconductor layer between the first intermediate layer and the light emitting layer. The first portion includes Alx1Iny1Ga1-x1-y1N (0<x1≦1, xw<x1, 0≦y1≦1, and ya<y1<yw). The second portion is in contact with the first intermediate layer between the first portion and the first intermediate layer. The second portion includes Alx2Iny2Ga1-x2-y2N (0<x2≦1, xw<x2, 0≦y2≦1, and ya≦y2<y1).
Various embodiments will be described hereinafter with reference to the accompanying drawings.
The drawings are schematic or conceptual; and the relationships between the thicknesses and the widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. Further, the dimensions and/or the proportions may be illustrated differently between the drawings, even for identical portions.
In the drawings and the specification of the application, components similar to those described in regard to a drawing thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.
The n-type semiconductor layer 10 includes a nitride semiconductor. The p-type semiconductor layer 20 is provided on a [0001]-direction side of the n-type semiconductor layer 10 and includes a nitride semiconductor. For example, a major surface 10a of the n-type semiconductor layer 10 opposing the p-type semiconductor layer 20 is, for example, the (0001) plane. However, as described below, the major surface 10a may not be the (0001) plane and may be tilted with respect to the crystal axis.
The light emitting layer is provided between the n-type semiconductor layer 10 and the p-type semiconductor layer 20. The light emitting layer 30 includes multiple barrier layers 31 and a well layer 32. The well layer 32 is provided between the multiple barrier layers 31. The barrier layers 31 include AlxbInybGa1-xb-ybN (0≦xb≦1 and 0≦yb≦1). The well layer 32 includes AlxwInywGa1-xw-ywN (0≦xw≦1, xw≦xb, 0<yw≦1, and yb<yw). The bandgap energy of the well layer 32 is less than the bandgap energy of the multiple barrier layers 31. The multiple barrier layers 31 include a p-side barrier layer 31p that is most proximal to the p-type semiconductor layer 20.
The first intermediate layer 45 is provided between the light emitting layer 30 and the p-type semiconductor layer 20. The first intermediate layer 45 includes AlxaInyaGa1-xa-yaN (0<xa≦1, xb≦xa, 0<ya≦1, and ya<yw). The bandgap energy of the first intermediate layer 45 is greater than the bandgap energy of the barrier layers 31.
The second intermediate layer 46 has a first portion 41 and a second portion 42. The first portion 41 contacts the p-side barrier layer 31p (the barrier layer 31 of the multiple barrier layers 31 most proximal to the p-type semiconductor layer 20) between the first intermediate layer 45 and the light emitting layer 30. The first portion 41 includes Alx1Iny1Ga1-x1-y1N (0<x1≦1, xw<x1, 0≦y1≦1, and ya<y1<yw). The second portion 42 contacts the first intermediate layer 45 between the first portion 41 and the first intermediate layer 45. The second portion 42 includes Alx2Iny2Ga1-x2-y2N (0<x2≦1, xw<x2, 0≦y2≦1, and ya≦y2<y1).
Thus, in the semiconductor light emitting device 110, a p-side intermediate layer 40 including the first intermediate layer 45 and the second intermediate layer 46 recited above is provided between the light emitting layer 30 and the p-type semiconductor layer 20. The boundary between the first intermediate layer 45 and the second intermediate layer 46 can be recognized in some cases by, for example, observation using an electron microscope, etc., and cannot be recognized in some cases. The composition of each of the layers is determined by, for example, evaluating using a three dimensional atom probe, etc.
The direction from the n-type semiconductor layer 10 toward the p-type semiconductor layer 20 is taken as a Z-axis direction. For example, in the semiconductor light emitting device 110, the light emitting layer 30 is provided on the n-type semiconductor layer 10; the second intermediate layer 46 is provided on the light emitting layer 30; the first intermediate layer 45 is provided on the second intermediate layer 46; and the p-type semiconductor layer 20 is provided on the first intermediate layer 45. The n-type semiconductor layer 10, the light emitting layer 30, the second intermediate layer 46, the first intermediate layer 45, and the p-type semiconductor layer 20 are stacked in the Z-axis direction in this order.
In the specification, the state of being “provided on” includes not only the state of being provided in direct contact but also the state of being provided with another component inserted therebetween. The state of being “stacked” includes not only the state of being overlaid with mutual contact but also the state of being overlaid with another component inserted therebetween.
The p-type semiconductor layer 20 opposes the n-type semiconductor layer 10 with the light emitting layer 30 interposed. In the specification, the state of being “opposed” includes not only the state of directly facing each other but also the state of indirectly facing each other with another component inserted therebetween.
To simplify the description hereinbelow, there are cases where a “lower side” or an “upper side” is referred to. The “lower side” corresponds to the n-type semiconductor layer 10 side; and the “upper side” corresponds to the p-type semiconductor layer 20 side.
The n-type semiconductor layer 10 may include, for example, a GaN layer containing an n-type impurity. The n-type impurity may include at least one selected from Si, Ge, Te, and Sn. The n-type semiconductor layer 10 includes, for example, an n-side contact layer.
The p-type semiconductor layer 20 may include, for example, a GaN layer containing a p-type impurity. The p-type impurity may include at least one selected from Mg, Zn, and C. The p-type semiconductor layer 20 includes, for example, a p-side contact layer.
The light emitting layer 30 may have, for example, a SQW structure (Single quantum well structure). In such a case, the number of the well layers 32 is one. The light emitting layer 30 may have, for example, a MQW structure (Multiple quantum well structure). In such a case, the number of the well layers 32 is two or more.
As illustrated in
In the semiconductor light emitting device 110, a current is supplied to the light emitting layer 30 via the n-type semiconductor layer 10 and the p-type semiconductor layer 20; and light is emitted by the light emitting layer 30. The peak wavelength of the light emitted from the light emitting layer 30 is, for example, not less than 365 nanometers (nm) and not more than 1550 nm. It is more favorable for the peak wavelength to be not less than 380 nm and not more than 600 nm. It is even more favorable for the peak wavelength to be not less than 400 nm and not more than 500 nm.
For example, the bandgap energy of the well layer 32 and the thickness of the well layer 32 are set such that the peak wavelength of the light emitted from the light emitting layer 30 is not less than 365 nm and not more than 1550 nm.
The well layer 32 may include, for example, InywGa1-ywN (0<yw≦1 and yb<yw). The In composition ratio yw of the well layer 32 is, for example, not less than 0.001 and not more than 1. The In composition ratio yw is, for example, not less than 0.03 and not more than 0.2. In such a case, the peak wavelength of the light emitted from the light emitting layer 30 is not less than 380 nm and not more than 600 nm. The In composition ratio yw is, for example, not less than 0.06 and not more than 0.185. In such a case, the peak wavelength of the light emitted from the light emitting layer 30 is not less than 400 nm and not more than 500 nm.
The thickness of the well layer 32 is, for example, not less than 1.5 nm and not more than 5 nm. In the case where multiple well layers 32 are provided, the composition and thickness may be different between the multiple well layers 32.
The barrier layers 31 may include, for example, InybGa1-ybN (0≦yb≦1). The In composition ratio yb of the barrier layers 31 is, for example, not more than 0.005. The barrier layers 31 may include, for example, GaN. The thickness of the barrier layers 31 is, for example, not less than 2.5 nm and not more than 7 nm. The composition and thickness may be different between the multiple barrier layers 31.
The semiconductor light emitting device 110 is, for example, an LED. The semiconductor light emitting device 110 may be a LD. In such a case, at least a portion of the n-type semiconductor layer 10 and at least a portion of the p-type semiconductor layer 20 function as waveguides of the light emitted from the light emitting layer 30.
In the embodiment, the p-side intermediate layer 40 (i.e., the first intermediate layer 45 and the second intermediate layer 46) having the configuration recited above is provided between the light emitting layer 30 and the p-type semiconductor layer 20. The bandgap energy of the first portion 41 of the second intermediate layer 46 on the light emitting layer 30 side is less than the bandgap energy of the second portion 42 of the second intermediate layer 46 on the p-type semiconductor layer 20 side.
For example, the bandgap energy of the second intermediate layer 46 has a slope along the Z-axis direction. For example, the In composition ratio of the second intermediate layer 46 decreases along the direction (the Z-axis direction) from the n-type semiconductor layer 10 toward the p-type semiconductor layer 20. For example, the In composition ratio of the second intermediate layer 46 decreases linearly along the Z-axis direction.
The injection efficiency of carriers into the light emitting layer 30 increases by providing the p-side intermediate layer 40 (i.e., the first intermediate layer 45 and the second intermediate layer 46) having such a configuration. Specifically, holes are effectively injected into the light emitting layer 30 from the p-type semiconductor layer 20 while suppressing the movement (the overflow) of the electrons from the light emitting layer 30 toward the p-type semiconductor layer 20. Thereby, the radiative recombination efficiency increases. According to the embodiment, a semiconductor light emitting device having a high efficiency can be provided.
The configuration recited above according to the embodiment is derived based on the following investigations.
To simplify the description hereinbelow, the case is described where the barrier layers 31 include GaN and the well layer 32 includes InGaN.
In the semiconductor light emitting device 131 as shown in
Similarly, considering the practical bandgap energy illustrated in
Conversely, the semiconductor light emitting device 132 which has the reverse slope configuration illustrated in
Considering the simple bandgap energy as shown in
However, in the actual device, the effects of the piezoelectric field and the applied electric field are large; and the bandgap energy profile is in the state illustrated in
Thus, even in the case where a reverse slope configuration is introduced to the p-side intermediate layer 40 to increase the injection efficiency of the holes in the semiconductor light emitting device 132, the injection efficiency of the holes remains low and the blocking effect of the electrons undesirably decreases in the actual device in which the piezoelectric field and the applied electric field exist.
On the other hand, the semiconductor light emitting device 133 which uses the p-side intermediate layer 40 having the forward slope illustrated in
Considering the simple bandgap energy in the semiconductor light emitting device 133 as shown in
However, in the actual device, the effects of the piezoelectric field and the applied electric field are large; and the bandgap energy profile is the state illustrated in
Thus, considering the simple bandgap energy in the semiconductor light emitting device 133 in which it is estimated that the injection efficiency of the holes is low, the injection efficiency of the holes increases in the actual configuration in which the piezoelectric field and the applied electric field exist. However, as recited above, the blocking effect of the electrons decreases.
Further, the semiconductor light emitting device 134 in which the second intermediate layer 46 and the first intermediate layer 45 are provided as the p-side intermediate layer 40 may be considered.
By providing the first intermediate layer 45 that has the high bandgap energy in the p-side intermediate layer 40 in addition to the second intermediate layer 46 that has the forward slope as shown in
In the semiconductor light emitting device 134 as shown in
Thus, in the semiconductor light emitting device 131, the luminous efficiency is low because the injection of the holes is suppressed by the p-side intermediate layer 40 for blocking the electrons. Conversely, in the semiconductor light emitting device 132 in which the p-side intermediate layer 40 that has the reverse slope is provided in expectation of the p-side intermediate layer 40 promoting the injection of the holes, the injection efficiency of the holes does not increase and the blocking effect of the electrons decreases in the actual device in which the piezoelectric field and the applied electric field exist.
Conversely, in the semiconductor light emitting device 133 in which the p-side intermediate layer 40 that has the forward slope is provided, the injection efficiency of the holes increases in the actual device in which the piezoelectric field and the applied electric field exist. However, the effective thickness of the barrier of the conduction band of the p-side intermediate layer 40 is thin; and the blocking effect of the electrons decreases.
In the semiconductor light emitting device 134 in which the first intermediate layer 45 and the second intermediate layer 46 that has the forward slope are provided as the p-side intermediate layer 40, the bottom of the bandgap energy Evp of the valence band is caused to be higher while obtaining the blocking effect of the electrons by maintaining the effective thickness of the barrier of the conduction band of the p-side intermediate layer 40 in the actual device in which the piezoelectric field and the applied electric field exist. Thereby, the injection efficiency of the holes increases.
From the investigation described above, it was found that the injection efficiency of the holes can be increased and a high luminous efficiency is obtained while the electrons are effectively blocked in the configuration in which the first intermediate layer 45 that has the large bandgap energy and the second intermediate layer 46 that has the forward slope are provided as the p-side intermediate layer 40.
Results of simulations of the characteristics of semiconductor light emitting devices having various configurations will now be described.
In the semiconductor light emitting devices 131 to 135 and 110 recited above, the n-type semiconductor layer 10 is n-type GaN; and the thickness of the n-type semiconductor layer 10 is 2000 nm. The barrier layers 31 are GaN; and the thickness of the barrier layers 31 is 15 nm. The well layers 32 are InGaN; and the thickness of the well layers 32 is 3 nm. The number of the well layers 32 is four. The p-type semiconductor layer 20 is p-type GaN; and the thickness of the p-type semiconductor layer 20 is 100 nm.
In the semiconductor light emitting device 131 as shown in
In the semiconductor light emitting device 132 which has the reverse slope configuration as shown in
In the semiconductor light emitting device 133 which has the forward slope configuration as shown in
In the semiconductor light emitting device 134 in which the p-side intermediate layer 40 of AlGaN including the second intermediate layer 46 and the first intermediate layer 45 is provided as shown in
In the semiconductor light emitting device 135 as well as shown in
In the semiconductor light emitting device 110 as well as shown in
It can be seen from
The internal quantum efficiency IQE of semiconductor light emitting device 133 containing the p-side intermediate layer 40 with forward slope configuration is higher than in device 131 with conventional structure. In particular, the internal quantum efficiency IQE of the semiconductor light emitting device 133 in the high current density region is high.
Also, in the semiconductor light emitting devices 134, 135, and 110 in which the p-side intermediate layer 40 including the second intermediate layer 46 and the first intermediate layer 45 is provided, in particular, the internal quantum efficiency IQE in the high current density region is higher than that of that of the semiconductor light emitting device 131. Further, the internal quantum efficiency IQE is high in the low current density region of the semiconductor light emitting devices.
Comparing the semiconductor light emitting devices 134, 135, and 110, in particular, the internal quantum efficiency at the low current density is extremely high in the semiconductor light emitting device 110 in which the Al composition ratio is constant and the In composition ratio of the second intermediate layer 46 has a slope compared to those of the semiconductor light emitting devices 134 and 135.
Thus, in the case of using the p-side intermediate layer 40 that includes the first intermediate layer 45 and the second intermediate layer 46 in which the bandgap energy has a forward slope, a higher internal quantum efficiency IQE is obtained in the low current density region for the configurations (the semiconductor light emitting devices 135 and 110, etc.) in which the quaternary AlInGaN are used as the p-side intermediate layer 40 than for the configuration (the semiconductor light emitting device 134) in which the three elements of AlGaN are used as the p-side intermediate layer 40. In the configuration in which the quaternary AlInGaN are used, a higher internal quantum efficiency is obtained for the configuration (the semiconductor light emitting device 110) in which the In composition ratio of the second intermediate layer 46 has the slope than for the configuration (the semiconductor light emitting device 135) in which the Al composition ratio of the second intermediate layer 46 has the slope.
Thus, according to the semiconductor light emitting device according to the embodiment, the injection efficiency of the charge can be increased; and a semiconductor light emitting device having a high efficiency can be provided.
The lattice mismatch with the GaN can be reduced by using the quaternary AlInGaN as the p-side intermediate layer 40. Therefore, for example, the crystal quality of the p-type semiconductor layer 20 can be improved. Thereby, the resistance of the p-type semiconductor layer 20 can be reduced. Also, the light absorption can be suppressed.
In the semiconductor light emitting device 110, the Al composition ratio x1 of the first portion 41, the Al composition ratio x2 of the second portion 42, and the Al composition ratio xa of the first intermediate layer 45 are 0.24; the In composition ratio y1 of the first portion 41 is 0.05; and the In composition ratio y2 of the second portion 42 and the In composition ratio ya of the first intermediate layer 45 are 0. Simulations of the internal quantum efficiency IQE for various values of x1, x2, xa, y1, y2, and ya show that results similar to those of the semiconductor light emitting device 110 are obtained for other values as well.
In the embodiment, the bandgap energy of the first portion 41 is not less than the bandgap energy of the p-side barrier layer 31p. For example, as in the semiconductor light emitting device 110 shown in
The Al composition ratio x2 of the second portion 42 is, for example, substantially the same as the Al composition ratio x1 of the first portion 41. For example, considering the manufacturing error, the measurement error, etc., the Al composition ratio x2 of the second portion 42 is within plus or minus (±) 10% of the Al composition ratio x1 of the first portion 41.
The Al composition ratio of the p-side intermediate layer 40 may be substantially constant. For example, the Al composition ratio x1 of the first portion 41 and the Al composition ratio x2 of the second portion 42 are substantially the same as the Al composition ratio xa of the first intermediate layer 45. For example, considering the manufacturing error, the measurement error, etc., the Al composition ratio x1 of the first portion 41 and the Al composition ratio x2 of the second portion 42 are within ±10% of the Al composition ratio xa of the first intermediate layer 45.
The Al composition ratio x1 of the first portion 41, the Al composition ratio x2 of the second portion 42, and the Al composition ratio xa of the first intermediate layer 45 are, for example, not less than 0.001 and not more than 0.5. For example, x1, x2, and xa may be not less than 0.01 and not more than 0.5. In the embodiment, the Al composition ratio xa of the first intermediate layer 45 may be different from the Al composition ratios (the Al composition ratio x1 and the Al composition ratio x2) of the second intermediate layer 46. The Al composition ratio x1 of the first portion 41 may be different from the Al composition ratio x2 of the second portion 42.
The In composition ratio y1 of the first portion 41 is, for example, not less than 0.005 and not more than 0.1. The In composition ratio y2 of the second portion 42 is, for example, less than 0.005 and not less than 0.
The Al composition ratio x1 of the first portion 41, the Al composition ratio x2 of the second portion 42, and the Al composition ratio xa of the first intermediate layer 45 are, for example, not less than 0.2 and not more than 0.5. For example, x1, x2, and xa may be not less than 0.3 and not more than 0.5. In such a case, the In composition ratio y1 of the first portion 41 is, for example, not less than 0.01 and not more than 0.07; and the In composition ratio y2 of the second portion 42 and the In composition ratio ya of the first intermediate layer 45 are, for example, less than 0.005. Here, y1, y2, and ya may be not less than 0.01. However, y2<y1.
For example, x1, x2, and xa are, for example, 0.32; y1 is, for example, 0.05; and y2 and ya are, for example, 0.
It is favorable for the Al composition ratio x2 of the second portion 42 to be not less than 4.5 times the In composition ratio y1 of the first portion 41. The Al composition ratio x1 of the first portion 41 may be not less than 4.5 times the In composition ratio y1 of the first portion 41. In the case where x1 and x2 are less than 4.5 times y1, that is, in the case where the In composition ratio of the second intermediate layer 46 is excessively high, the mismatch of the lattice spacing increases, which leads to poorer crystal quality. In the case where x1 and x2 are not less than 4.5 times y1, the mismatch of the lattice spacing can be small; and it becomes easier to maintain high crystal quality.
In the embodiment, the thickness of the first intermediate layer 45 is not less than 0.5 times the thickness of the second intermediate layer 46 and not more than 2 times the thickness of the second intermediate layer 46. For example, the thickness of the first intermediate layer 45 is not less than the thickness of the second intermediate layer 46. Thereby, the effective thickness of the barrier to the electrons can be maintained. Thereby, the blocking effect of the electrons can be realized sufficiently.
The thickness of the first intermediate layer 45 is, for example, not less than 5 nm and not more than 30 nm. In the case where the thickness of the first intermediate layer 45 is less than 5 nm, the effective thickness of the barrier to the electrons becomes excessively thin. In the case where the thickness of the first intermediate layer 45 exceeds 30 nm, for example, the operating voltage becomes too high.
The thickness of the second intermediate layer 46 is, for example, not less than 1 nm and not more than 20 nm. In the case where the thickness of the second intermediate layer 46 is less than 1 nm, for example, the control of the In composition ratio of the second intermediate layer 46 becomes difficult; and it becomes difficult to obtain the desired bandgap energy profile. In the case where the thickness of the second intermediate layer 46 exceeds 20 nm, for example, the operating voltage becomes too high.
In the embodiment, the p-side intermediate layer 40 may contain a p-type impurity. For example, Mg is used as the p-type impurity.
It is favorable for the concentration of the p-type impurity of the second portion 42 to be higher than the concentration of the p-type impurity of the first portion 41. Thereby, the injection efficiency of the holes into the light emitting layer 30 is increased further. In such a case, the first portion 41 may substantially not contain the p-type impurity.
The concentration of the p-type impurity (e.g., Mg) of the first portion 41 is, for example, less than 1×1019 cm−3 and not less than 1×1018 cm−3 (e.g., 5×1018 cm−3). The concentration of the p-type impurity (e.g., Mg) of the second portion 42 is, for example, less than 1×1020 cm−3 and not less than 1×1019 cm−3 (e.g., 5×1019 cm−3).
It is favorable for the concentration of the p-type impurity (e.g., Mg) of the first intermediate layer 45 to be not less than the concentration of the p-type impurity (e.g., Mg) of the second intermediate layer 46. Thereby, the injection efficiency of the holes into the light emitting layer 30 is increased further.
As illustrated in
In the semiconductor light emitting device 112 as shown in
Due to the method for measuring the composition, there are cases where the change of the composition that is measured changes more gradually than the actual change of the composition. Such cases also are included in the embodiment.
In the embodiment, the configuration of the p-side intermediate layer 40 is set to reflect the characteristics based on the piezoelectric field. The effect of the piezoelectric field is large when, for example, the In composition ratio yw of the well layer 32 is relatively high. Therefore, in the embodiment, the effect of increasing the luminous efficiency increases when the In composition ratio yw is relatively high, e.g., not less than 0.06 and not more than 0.185. In the embodiment, the peak wavelength of the light emitted from the light emitting layer 30 is, for example, not less than 400 nm and not more than 500 nm. In such a case, the effect of increasing the luminous efficiency becomes particularly large.
In the embodiment as described above, the p-type semiconductor layer 20 is disposed, for example, on the [0001]-direction side of the n-type semiconductor layer 10. The major surface 10a of the n-type semiconductor layer 10 opposing the p-type semiconductor layer 20 may be tilted at a constant angle from the (0001) plane.
It can be seen from
Accordingly, in the embodiment, the angle θ1 between the axis perpendicular to the major surface 10a of the n-type semiconductor layer 10 opposing the light emitting layer 30 and the <0001> direction of the n-type semiconductor layer 10 is not less than 0 degrees and not more than 40 degrees. In such a case, the piezoelectric field of the direction (the polarity) described above occurs; the profile of the bandgap energy of the semiconductor layer is formed according to the piezoelectric field; and the effects of the p-side intermediate layer 40 according to the embodiment are appropriately obtained. Thus, the major surface 10a of the n-type semiconductor layer 10 may be tilted from the (0001) plane.
The case where the angle θ1 is 0 degrees corresponds to the state in which the axis perpendicular to the major surface 10a of the n-type semiconductor layer 10 opposing the light emitting layer 30 is parallel to the <0001> direction of the n-type semiconductor layer 10.
The major surface 10a of the n-type semiconductor layer 10 is, for example, the c plane. For example, a not-shown buffer layer is formed on a substrate (not shown); and the n-type semiconductor layer 10, the light emitting layer 30, the p-side intermediate layer 40, and the p-type semiconductor layer 20 are sequentially formed on the buffer layer. The substrate recited above may include, for example, a c-plane sapphire substrate. Or, for example, a silicon (Si) substrate of one selected from (110), (111), and (100) may be used as the substrate. The substrate and the buffer layer may be removed after the formation of these layers.
In the embodiment, the method for depositing the semiconductor layers may include any method such as metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy, etc.
According to the embodiment, the injection efficiency of the charge is increased; and a semiconductor light emitting device having a high efficiency can be provided.
In the specification, “nitride semiconductor” includes all compositions of semiconductors of the chemical formula BxInyAlzGa1-x-y-zN (0≦x<1, 0≦y≦1, 0≦z≦1, and x+y+z≦1) for which the composition ratios x, y, and z are changed within the ranges respectively. “Nitride semiconductor” further includes group V elements other than N (nitrogen) in the chemical formula recited above, various elements added to control various properties such as the conductivity type and the like, and various elements included unintentionally.
In the specification of the application, “perpendicular” and “parallel” refer to not only strictly perpendicular and strictly parallel but also include, for example, the fluctuation due to manufacturing processes, etc. It is sufficient to be substantially perpendicular and substantially parallel.
Hereinabove, embodiments of the invention are described with reference to specific examples. However, the invention is not limited to these specific examples. For example, one skilled in the art may similarly practice the invention by appropriately selecting specific configurations of components included in semiconductor light emitting devices such as n-type semiconductor layers, p-type semiconductor layers, light emitting layers, well layers, barrier layers, p-side intermediate layers, first intermediate layers, second intermediate layers, etc., from known art; and such practice is included in the scope of the invention to the extent that similar effects are obtained.
Further, any two or more components of the specific examples may be combined within the extent of technical feasibility and are included in the scope of the invention to the extent that the purport of the invention is included.
Moreover, all semiconductor light emitting devices practicable by an appropriate design modification by one skilled in the art based on the semiconductor light emitting devices described above as embodiments of the invention also are within the scope of the invention to the extent that the spirit of the invention is included.
Various other variations and modifications can be conceived by those skilled in the art within the spirit of the invention, and it is understood that such variations and modifications are also encompassed within the scope of the invention.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.
Number | Date | Country | Kind |
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2012-168940 | Jul 2012 | JP | national |