Patent Application
20130278165
This application claims foreign priority from Japanese Patent Application No. 2012-096410 filed on Apr. 20, 2012, the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The invention relates to a semiconductor light source lighting circuit for lighting a semiconductor light source such as an LED (Light Emitting Diode).
2. Related Art
In recent years, an LED having a longer life and lower power consumption has been used as a vehicular lamp such as a headlamp, instead of a conventional halogen lamp having a filament. Since a degree of light emission (e.g. a brightness) of the LED depends on a current flowing through the LED, it is necessary to provide a lighting circuit for adjusting the current flowing through the LED in order to use the LED as a light source.
Such a lighting circuit usually includes a switching regulator for generating the current flowing through the LED using a switching element and a control circuit for controlling the switching regulator. The control circuit includes an error amplifier and performs a feedback control such that the current flowing through the LED is to be stable (see, for example, JP-A-2010-170704).
In order to reduce a circuit size by improving a performance of the feedback control, a digitization of the control circuit may be conceivable. However, as a result of the digitization, there may be a possibility that an oscillation occurs in the current flowing through the LED by an interaction between a counting operation in the feedback control and a switching operation of the switching regulator.
One or more embodiments provide a semiconductor light source lighting circuit which is capable of suppressing an oscillation of a drive current even when the circuit is digitized.
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The same or similar components, members and signals shown in each drawing are denoted by the same reference numerals and a duplicated description thereof is appropriately omitted. In each drawing, some of the members that are not important for descriptive purposes are omitted. In addition, the reference numerals used to denote voltage, current or resistance or the like are sometimes used to represent respective values of voltage, current or resistance as necessary.
In this specification, a “state in which a member A is connected to a member B” includes not only the case where the member A and the member B are physically directly connected to each other but also the case where the member A and the member B are indirectly connected to each other via another member which does not affect the electric connection state therebetween. Likewise, a “state in which a member C is provided between a member A and a member B” includes not only the case where the member A and the member C or the member B and the member C are directly connected to each other but also the case where the member A and the member C or the member B and the member C are indirectly connected via another member which does not affect the electric connection state therebetween.
According to embodiments, a semiconductor light source light circuit may include a switching regulator which generates a drive current flowing through an LED using a switching element and a control circuit which performs a current feedback control for the ON/OFF of the switching element such that the magnitude of the drive current approximates to a target value. In the current feedback control, a control value such as an amount of error may be digitally held and updated. A counting cycle of such a digital control value may be determined by the ON/OFF cycle of the switching element of the switching regulator. By doing so, it would be possible to avoid a situation where the ON/OFF cycle of the switching element and the counting cycle of the digital control value are too close and therefore it would be possible to suppress an oscillation of the drive current.
The engine control unit 20 is a micro controller for performing a comprehensive electric control of the vehicle. The engine control unit 20 is connected to the battery 30 via a switch SW. As the switch SW is turned on, the engine control unit 30 receives a battery voltage Vbat from the battery 30. The engine control unit 20 supplies the DC battery voltage Vbat as the input voltage Vin to the semiconductor light source lighting circuit 100. The engine control unit 20 also supplies a fixed voltage, that is, a ground potential VGND (=0 V) to the semiconductor light source lighting circuit 100.
When a sudden load is applied to the battery 30, such as during start up of an engine, the battery voltage Vbat is decreased. And, when the load is eliminated, the battery voltage Vbat is increased. Correspondingly, the input voltage Vin is variable.
The semiconductor light source lighting circuit 100 includes a switching regulator 104, a control circuit 102 to control the switching regulator 104 and an external variable resistor 60.
The switching regulator 104 converts an input voltage Vin inputted from the engine control unit 20 into an output voltage Vout suitable for a forward voltage Vf of the LED 40 using a switching element 122 and applies the output voltage to an anode of the LED 40. The switching element 122 may be a transistor such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor). From the viewpoint of the current, the switching regulator 104 generates a drive current flowing through the LED 40 from the input voltage Vin using the switching element 122. The ground potential of the switching regulator 104 is supplied from the engine control unit 20.
The control circuit 102 controls the ON/OFF of the switching element 122 so that the magnitude of a drive current ILED approximates to a target value. The control circuit 102 includes a current detection part 112, a first reference voltage source 114, an error comparator 116, an up/down counter 118, a D/A converter 120, a drive circuit 106, a control clock selection circuit 150, a control divider circuit 110, a drive oscillator 130, a control oscillator 140, a discrimination circuit 160 and a switching circuit 180. The control circuit 102 may be realized by a micro computer.
The current detection part 112 detects the magnitude of the drive current ILED. The current detection part 112 is a current detection resistor through which the drive current ILED flows, for example. The current detection part 112 generates a detection voltage Vd according to the magnitude of the drive current ILED and applies the detection voltage Vd to a non-inverting input terminal of the error comparator 116. The current detection part 112 supplies the detection voltage Vd to the control clock selection circuit 150. The detection voltage Vd is generated on the basis of the fixed voltage such as the ground potential.
The first reference voltage source 114 generates a first reference voltage Vref1 corresponding to a target value of the magnitude of the drive current ILED and applies the first reference voltage Vref1 to an inverting input terminal of the error comparator 116. The first reference voltage source 114 supplies the first reference voltage Vref1 to the control clock selection circuit 150. The first reference voltage Vref1 is generated on the basis of the fixed voltage.
The error comparator 116 compares the detection voltage Vd and the first reference voltage Vref1. Specifically, the error comparator 116 compares the magnitude of the drive current ILED represented by the detection voltage Vd and the target value represented by the first reference voltage Vref1. The error comparator 116 generates an error signal S2 that is asserted or negated in accordance with the magnitude relation between the detection voltage Vd and the first reference voltage Vref1 and outputs the error signal to the up/down counter 118. In particular, the error signal S2 is asserted when Vd≧Vref1 and the voltage of the error signal S2 becomes high level. And, the error signal S2 is negated when Vd<Vref1 and the voltage of the error signal S2 becomes low level.
The up/down counter 118 counts a control digital value in a count direction determined by the comparison result of the error comparator 116. An element having the same function as 74-series ‘191 which is a standard logic IC, for example, may be employed as the up/down counter 118. The up/down counter 118 includes an U/D control terminal 118a to which the error signal S2 is inputted, a clock pulse input terminal 118b to which a control clock signal S3 is inputted and output terminals 118c, the number of which corresponds to the number of bits of the control digital value to be counted.
In a case where the voltage of the error signal S2 becomes high level, the up/down counter 118 counts up the control digital value in accordance with the transition of the control clock signal S3, that is, each time when a rising edge appears in the control clock signal S3. In a case where the voltage of the error signal S2 becomes low level, the up/down counter 118 counts down the control digital value each time when a rising edge appears in the control clock signal S3. The up/down counter 118 outputs a present control digital value from the output terminal 118c to the D/A converter 120.
The D/A converter 120 converts the control digital value outputted from the output terminal 118c to a duty ratio setting signal S4 which has a analog voltage according to the control digital value. The digital-analog conversion processing itself in the D/A converter 120 may be performed using a conventional digital-analog conversion technique. The D/A converter 120 outputs the duty ratio setting signal S4 to the drive circuit 106. The duty ratio setting signal S4 has higher voltage as the control digital value becomes greater.
The drive circuit 106 controls the ON/OFF duty ratio of the switching element 122 based on the duty ratio setting signal S4 obtained as a result of the conversion by the D/A converter 120. The drive circuit 106 compares the duty ratio setting signal S4 and a sawtooth wave signal S5 whose voltage is changed to a sawtooth wave form at the drive frequency f2. The drive circuit 106 generates an element control signal S7 whose voltage is changed to a rectangular wave form at the drive frequency f2, based on the result of comparison. The element control signal S7 has a duty ratio according to the voltage of the duty ratio setting signal S4. High duty of the element control signal S7 becomes smaller as the voltage of the duty ratio setting signal S4 becomes higher. The drive circuit 106 outputs the generated element control signal S7 to a control terminal (that is, a gate) of the switching element 122. Consequently, as the control digital value becomes greater, the on-duty of the switching element 122 becomes smaller and acts in a direction to decrease the drive current MED. In this way, a current feedback control to approximate the drive current ILED to the target value is performed in the control circuit 102.
The ON/OFF frequency of the switching element 122 is the drive frequency f2 and the ON/OFF cycle thereof is 1/f2.
The drive oscillator 130 generates a sawtooth wave signal S5 having the drive frequency f2 according to the magnitude of a drive frequency setting current Ic and outputs the sawtooth wave signal to the drive circuit 106. The drive oscillator 130 generates a drive clock signal S15 of rectangular wave having the drive frequency f2 and outputs the drive clock signal to the control clock selection circuit 150. A technique to generate the sawtooth wave or the rectangular wave having the frequency according to the current value is well-known itself by a relaxation oscillator or the like, for example.
The control oscillator 140 is an oscillator which is provided independent of the drive oscillator 130. The control oscillator generates a clock source signal S8 and supplies the clock source signal to the control divider circuit 110. The voltage of the clock source signal S8 is changed to the rectangular wave form in a timing frequency f3 of about 2 MHz.
The control divider circuit 110 generates a first division signal S11, a second division signal S12, a third division signal S13 and a fourth division signal S14 which are obtained by respectively dividing the clock source signal S8 at predetermined division ratios of N1, N2, N3 and N4 (N1>N2, N3>N4). The control divider circuit 110 output the first division signal S11 and the second division signal S12 to the switching circuit 180 and outputs the third division signal S13 and the fourth division signal S14 to the control clock selection circuit 150. The control divider circuit 110 may be configured by one or more counters, or the like. As an example, N1=512, N2=32, N3=4 and N4=1. Specifically, the frequency of the first division signal S11 is about 3.9 kHz, the frequency of the second division signal S12 is about 62.5 kHz, the frequency of the third division signal S13 is about 500 kHz and the frequency of the fourth division signal S14 is about 2 MHz.
The discrimination circuit 160 discriminates the magnitude relation between the drive frequency f2 and a frequency threshold fth. The discrimination circuit 160 generates a drive frequency setting current Ic according to the resistance value of the external variable resistor 60 connected to an external resistor terminal 100a of the control circuit 102, supplies the drive frequency setting current Ic to the drive oscillator 130 and compares the drive frequency f2 determined by the resistance value with the frequency threshold fth. In the exemplary embodiment, a resistance value which causes the drive frequency f2 to be 300 kHz (±100 kHz) and a resistance value which causes the drive frequency f2 to be 2 MHz are considered as the resistance value of the external variable resistor 60. The frequency threshold fth is set to about 1 MHz.
Generally, the circuit element becomes smaller as the drive frequency f2 becomes higher. However, in this case, a noise performance is degraded and an amount of heat to be generated is increased. Accordingly, an optimum drive frequency f2 is different for each application. For this reason, the semiconductor light source lighting circuit 100 is so configured that the drive frequency f2 can be changed by the resistance value of the external variable resistor 60. Thereby, a user can set the drive frequency f2 to an optimal value according to the applications without changing the interior of the control circuit 102.
The discrimination circuit 160 generates a discrimination signal S1 and outputs the discrimination signal to the switching circuit 180. The discrimination signal S1 becomes high level when the drive frequency f2 is greater than the frequency threshold fth and becomes low level when the drive frequency f2 is less than the frequency threshold fth.
The switching circuit 180 switches the counting speed of the up/down counter 118 when the magnitude of the drive current ILED is relatively close to the target value, based on the discrimination signal S1. The switching circuit 180 outputs the second division signal S12 as the steady clock signal S10 to the control clock selection circuit 150 when the drive frequency f2 is greater than the frequency threshold fth. The switching circuit 180 outputs the first division signal S11 as the steady clock signal S10 to the control clock selection circuit 150 when the drive frequency f2 is less than the frequency threshold fth.
The current mirror circuit 228 includes a first pnp-type bipolar transistor 208, a second pnp-type bipolar transistor 210, a third pnp-type bipolar transistor 212, a sixth resistor 220, a seventh resistor 222 and an eighth resistor 224. These circuit elements are connected to each other so as to configure a conventional current mirror circuit. The current mirror circuit 228 uses a setting current I1 as an input and uses an output current I2 and the drive frequency setting current Ic as an output. The current mirror circuit 228 causes the magnitude of the output current I2 and the drive frequency setting current Ic to be substantially same as the magnitude of the setting current I1. The current mirror circuit 228 supplies the drive frequency setting current Ic to the drive oscillator 130. As the output current I2 flows through the fifth resistor 218, the output current is converted into a drive frequency setting voltage Vc. Since the drive frequency f2 is determined by the magnitude of the drive frequency setting current Ic, the drive frequency setting voltage Vc corresponds to the drive frequency f2.
The voltage regulator circuit 230 is operated so that the voltage applied to the external resistor terminal 100a approximates to a second reference voltage Vref2 generated by a second reference voltage source 214. The voltage regulator circuit 230 includes an operational amplifier 202, a first npn-type bipolar transistor 206 and a second reference voltage source 214. The second reference voltage Vref2 is applied to a non-inverting input terminal of the operational amplifier 202 and an inverting input terminal of the operational amplifier 202 is connected to the external resistor terminal 100a. The setting current I1 is inputted to a collector of the first npn-type bipolar transistor 206 and a base of the first npn-type bipolar transistor is connected to an output terminal of the operational amplifier 202. An emitter of the first npn-type bipolar transistor 206 is connected to the external resistor terminal 100a.
By the action of the voltage regulator circuit 230, the voltage of the external resistor terminal 100a is maintained substantially constant in the vicinity of the second reference voltage Vref2 even when the resistance value of the external variable resistor 60 is varied. When the resistance value of the external variable resistor 60 is represented as “RV”, a formula of I1=Vref2/RV is established. Specifically, it is possible to change the magnitude of the setting current I1, that is, the drive frequency f2 by changing the resistance value of the external variable resistor 60.
The comparison circuit 232 compares the drive frequency f2 and the frequency threshold fth. The comparison circuit 232 includes a fifth comparator 204, a third reference voltage source 216 and a ninth resistor 226. The third reference voltage source 216 generates a third reference voltage Vref3 corresponding to the frequency threshold fth and applies the third reference voltage to an inverting input terminal of the fifth comparator 204. A drive frequency setting voltage Vc is applied to a non-inverting input terminal of the fifth comparator 204. The ninth resistor 226 is provided between a power supply voltage terminal and an output terminal of the fifth comparator 204 and serves as a pull-up resistor for the fifth comparator 204.
The fifth comparator 204 compares the drive frequency setting voltage Vc and the third reference voltage Vref3. Specifically, the fifth comparator 204 compares the drive frequency f2 represented by the drive frequency setting voltage Vc and the frequency threshold fth represented by the third reference voltage Vref3. The fifth comparator 204 generates the above-described discrimination signal S1 representing the comparison result.
The switching circuit 180 includes a first AND gate 302, an eighth AND gate 304, a third OR gate 306 and a fifth inverter 308. The fifth inverter 308 inverts the level of the discrimination signal S1. The first AND gate 302 outputs a logical product of the second division signal S12 and the discrimination signal S1. The eighth AND gate 304 outputs a logical product of the output signal of the fifth inverter 308 and the first division signal S11. The third OR gate 306 outputs a logical sum of the output signal of the first AND gate 302 and the output signal of the eighth AND gate 304 as the steady clock signal S10 to the control clock selection circuit 150.
By returning to
Function 1 is to generate the control clock signal S3 of rectangular wave having the frequency according to the magnitude relation between the drive frequency f2 and the frequency threshold fth in a case where the magnitude of the drive current ILED is relatively close to the target value. When this function is implemented, the up/down counter 118 counts the control digital value at a speed which is determined by the drive frequency f2. Particularly, the up/down counter 118 counts the digital value faster as the drive frequency f2 becomes higher.
Function 2 is to cause the frequency of the control clock signal S3 to be a frequency which is substantially independent of the drive frequency f2 and higher than the frequency thereof when the magnitude of the drive current ILED is relatively close to the target value, in a case where the magnitude of the drive current ILED is relatively far from the target value. When this function is implemented, the up/down counter 118 performs a counting operation based on the clock source signal S8 which is outputted from the control oscillator 140 different from the drive oscillator 130. Further, the up/down counter 118 counts the control digital value faster than a case where the magnitude of the drive current ILED is relatively close to the target value.
The control clock selection circuit 150 compares the detection voltage Vd and the first reference voltage Vref1 to determine whether the difference or ratio between the magnitude of the drive current ILED and the target value is within a predetermined error range or not. The error range contains a value of 0 in a case of the difference and a value of 1 in a case of the ratio. When it is determined that the difference or ratio is within the predetermined error range, the control clock selection circuit 150 selects the steady clock signal S10 among the steady clock signal S10, the third division signal S13 and the fourth division signal S14 and outputs the selected steady clock signal S10 as the control clock signal S3. When it is determined that the difference or ratio is not within the predetermined error range, the control clock selection circuit 150 selects the third division signal S13 or the fourth division signal S14 among the steady clock signal S10, the third division signal S13 and the fourth division signal S14, depending on the value of the difference or ratio. In particular, the control clock selection circuit 150 selects a signal of higher frequency as the difference or ratio between the magnitude of the drive current ILED and the target value becomes greater.
Table 1 shows a selection operation of the control clock selection circuit 150.
In Table 1, the drive current ILED range of “0.73 A to 0.97 A” corresponds to the error range of “−0.12 A to 0.12 A” for the difference between the magnitude of the drive current ILED and the target value “0.85 A”. The drive current ILED range of “0.97 A to 1.21 A” corresponds to a first deviation range of “0.12 A to 0.36 A” for the difference between the magnitude of the drive current ILED and the target value “0.85 A”. The drive current ILED range of “not less than 1.21 A” corresponds to a second deviation range of “not less than 0.36 A” for the difference between the magnitude of the drive current ILED and the target value “0.85 A”. The drive current ILED range of “0.49 A to 0.73 A” corresponds to a third deviation range of “−0.36 A to −0.12 A” for the difference between the magnitude of the drive current ILED and the target value “0.85 A”. The drive current ILED range of “not more than 0.49 A” corresponds to a fourth deviation range of “not more than −0.36 A” for the difference between the magnitude of the drive current ILED and the target value “0.85 A”.
An adjustment circuit 504 receives and adjusts the detection voltage Vd inputted to the control clock selection circuit 150 and generates a processed detection voltage Vd. Each circuit constant of the first voltage-dividing circuit 506, the second voltage-dividing circuit 508, the third voltage-dividing circuit 510 and the adjustment circuit 504 is set so that V1>Vd′≧V2 corresponds to the error range, Vref1>Vd′≧>V1 corresponds to the first deviation range, Vd′≧Vref1 corresponds to the second deviation range, V2>Vd′≧V3 corresponds to the third deviation range and V3>Vd′ corresponds to the fourth deviation range.
A first comparator 512 compares the processed detection voltage Vd′ and the first reference voltage Vref1 and generates a first comparison signal S17 which becomes high level when the processed detection voltage Vd′≧ the first reference voltage Vref1 and becomes low level in other cases. A second comparator 514 compares the processed detection voltage Vd′ and the first divided voltage V1 and generates a second comparison signal S18 which becomes high level when the processed detection voltage Vd′≧ the first divided voltage V1 and becomes low level in other cases. A third comparator 516 compares the processed detection voltage Vd′ and the second divided voltage V2 and generates a third comparison signal S19 which becomes high level when the processed detection voltage Vd′≧ the second divided voltage V2 and becomes low level in other cases. A fourth comparator 518 compares the processed detection voltage Vd′ and third divided voltage V3 and generates a fourth comparison signal S20 which becomes high level when the processed detection voltage Vd′≧ the third divided voltage V3 and becomes low level in other cases. A first resistor 520, a second resistor 522, a third resistor 524 and a fourth resistor 526 are respectively pull-up resistors for the first comparator 512, the second comparator 514, the third comparator 516 and the fourth comparator 518.
A first inverter 528, a second inverter 532, a third inverter 534 and a fourth inverter 538 respectively invert the levels of the first comparison signal S17, the second comparison signal S18, the third comparison signal S19 and the fourth comparison signal S20.
A second AND gate 530 outputs a logical product of the output signal of the first inverter 528 and the second comparison signal S18. A third AND gate 536 outputs a logical product of the output signal of the third inverter 534 and the fourth comparison signal S20. A first OR gate 540 outputs a logical sum of the first comparison signal S17 and the output signal of the fourth inverter 538. A second OR gate 542 outputs a logical sum of the output signal of the second AND gate 530 and the output signal of the third AND gate 536. A seventh AND gate 544 outputs a logical product of the output signal of the second inverter 532 and the third comparison signal S19.
The output signal of the first OR gate 540, the output signal of the second OR gate 542 and the output signal of the seventh AND gate 544 are respectively inputted to a data terminal of a first D-type flip-flop 560, a data terminal of a second D-type flip-flop 562 and a data terminal of a third D-type flip-flop 564. The drive clock signal
S15 is commonly inputted to a clock terminal of the first D-type flip-flop 560, a clock terminal of the second D-type flip-flop 562 and a clock terminal of the third D-type flip-flop 564. By these three D-type flip-flops, the frequency switching of the control clock signal S3 and the ON/OFF of the switching element 122 are synchronized.
A fourth AND gate 546 outputs a logical product of the fourth division signal S14 and a signal outputted from a non-inverting output terminal of the first D-type flip-flop 560. A fifth AND gate 548 outputs a logical product of the third division signal S13 and a signal outputted from a non-inverting output terminal of the second D-type flip-flop 562. A sixth AND gate 550 outputs a logical product of the steady clock signal S10 and a signal outputted from a non-inverting output terminal of the third D-type flip-flop 564.
A fourth OR gate 552 outputs a logical sum of the output signal of the fourth AND gate 546 and the output signal of the fifth AND gate 548. A fifth OR gate 554 outputs a logical sum of the output signal of the fourth OR gate 552 and the output signal of the sixth AND gate 550.
The control clock selection circuit 150 outputs the output signal of the fifth OR gate 554 as the control clock signal S3.
For example, when V1>Vd′>V2, the first comparison signal S17 and the second comparison signal S18 become low level and the third comparison signal S19 and the fourth comparison signal become high level. Since the first comparison signal S17 is low level and the output signal of the fourth inverter 538 is low level, the output signal of the first OR gate 540 becomes low level. Accordingly, the output signal of the fourth AND gate 546 becomes low level, regardless of the fourth division signal S14. In addition, since the output signal of the second OR gate 542 is also low level, the output signal of the fifth AND gate 548 becomes low level, regardless of the third division signal S13. On the other hand, since the output signal of the seventh AND gate 544 becomes high level, the output signal of the sixth AND gate 550 becomes the steady clock signal S10. As a result, the steady clock signal S10 is outputted as the control clock signal S3.
When the drive frequency f2 is greater than the frequency threshold fth, the steady clock signal S10 becomes the second division signal S12 and the frequency thereof becomes about 62.5 kHz. On the other hand, when the drive frequency f2 is less than the frequency threshold fth, the steady clock signal S10 becomes the first division signal S11 and the frequency thereof becomes about 3.91 kHz.
In this way, the selection operation shown in Table 1 is implemented by the control clock selection circuit 150 shown in
An operation of the semiconductor light source lighting circuit 100 having the above configurations will be described.
At time t1, the input voltage Vin begins to transition from 13 V to 16 V. In response to the rise of the input voltage Vin, the drive current ILED starts to rise from 0.85 A, which is the target value. Since the drive current ILED becomes higher than the target value, the up/down counter 118 counts up the control digital value. The control clock selection circuit 150 selects the steady clock signal S10 as the control clock signal S3 and the frequency of the control clock signal S3 is a value corresponding to the drive frequency f2. Here, the drive frequency f2 is set to 300 kHz. Accordingly, the frequency of the control clock signal S3 is about 3.91 kHz. The count-up speed is slower than the rising speed of the drive current ILED according to the rise of the input voltage Vin and the drive current ILED continues to rise.
At time t2, the difference between the magnitude of the drive current ILED and the target value falls within the first deviation range. That is, the drive current ILED exceeds 0.97 A. The control clock selection circuit 150 selects the third division signal S13 as the control clock signal S3 and the frequency of the control clock signal S3 becomes about 500 kHz. Accordingly, the count-up of the up/down counter 118 becomes faster.
At time t3, the difference between the magnitude of the drive current ILED and the target value falls within the second deviation range. That is, the drive current ILED exceeds 1.21 A. The control clock selection circuit 150 selects the fourth division signal S14 as the control clock signal S3 and the frequency of the control clock signal S3 becomes about 2 MHz. Accordingly, the count-up of the up/down counter 118 becomes even faster.
At time t4, the drive current ILED is less than 1.21 A. The control clock selection circuit 150 selects the third division signal S13 as the control clock signal S3 and the frequency of the control clock signal S3 becomes about 500 kHz. Accordingly, the count-up of the up/down counter 118 becomes slower.
At time t5, the drive current ILED is less than 0.97 A. The control clock selection circuit 150 selects the steady clock signal S10 as the control clock signal S3 and the frequency of the control clock signal S3 becomes about 3.91 kHz. Accordingly, the count-up speed of the up/down counter 118 becomes equivalent to the speed prior to time t1.
The above description is similarly applied to even when the input voltage Vin is changed from 16 V to 13 V, except that the direction of change is reversed.
According to the semiconductor light source lighting circuit 100 of the exemplary embodiment, the count-up speed of the up/down counter 118 is determined in accordance with the drive frequency f2. Accordingly, the frequency of count can be set so that the frequency of count is not too close to the drive frequency f2. Thereby, it is possible to suppress the oscillation of the drive current ILED by the interaction between a switching operation of the switching regulator 104 and an update of the control value in the current feed control.
When there is no action for the sudden change of the input voltage Vin, the change in the control digital value cannot keep up with the change in the input voltage Vin and thus large overshoot or undershoot may be caused. The change in the control digital value and the change in the drive current ILED in this case are indicated by a broken line in
On the contrary, in the semiconductor light source lighting circuit 100 of the exemplary embodiment, the up/down counter 118 counts the control digital value faster as the difference between the magnitude of the drive current ILED and the target value becomes larger. Specifically, the up/down counter 118 is operated at a relatively low-frequency clock when the drive current ILED is close to the target value but is operated at a high-frequency clock as the detected value of the drive current ILED is far from the target value, so that the drive current ILED can be quickly converged to the target value. By doing so, the control digital value can be quickly changed while keeping up with the change in the input voltage Vin even when the input voltage Vin is suddenly changed. As a result, it is possible to suppress the overshoot or undershoot and therefore it is possible to prevent the deterioration of the LED 40.
From the viewpoint of reduction of the circuit size, it is desirable that the element control signal related to the switching element 122 and the control clock signal related to the up/down counter are generated by the same oscillator. However, in this case, the control frequency of the up/down counter is also decreased in conjunction with the drive frequency when the drive frequency f2 is decreased. Accordingly, when the drive frequency f2 is low and also the input voltage Vin is suddenly changed, there is a possibility that it is difficult to respond to the sudden change of the input voltage and therefore the overshoot or undershoot of the drive current ILED can be caused, even if the up/down counter is quickly counted in response to an increase in the difference between the drive current ILED and the target value. For example, 2 MHz and 300 kHz are assumed as the drive frequency f2. In a case where the drive frequency f2 is set to 2 MHz, the control frequency f2 can be increased to about 2 MHz by quickly counting the up/down counter. However, in a case where the drive frequency f2 is set to 300 kHz, a counting speed of the up/down counter has a limit of about 300 kHz.
Accordingly, in the semiconductor light source lighting circuit 100 according to the exemplary embodiment, the drive oscillator 130 for driving the switching element 122 and the control oscillator 140 for the up/down counter 118 are separately provided. When the difference between the magnitude of the drive current ILED and the target value is relatively large, the semiconductor light source lighting circuit 100 generates the control clock signal S3 faster using the clock source signal S8 outputted by the control oscillator 140. At this time, the frequency of the control clock signal S3 does not depend on the drive frequency f2. Thereby, the up/down counter 118 can count the control digital value fast enough to respond to the sudden change of the input voltage Vin, even if the drive frequency f2 is low. As a result, it is possible to suppress occurrence of the overshoot or undershoot of the drive current ILED, thereby maintaining the light-emitting performance of the LED 40.
In the semiconductor light source lighting circuit 100, occurrence frequency of the sudden change of the input voltage Vin is generally not very high. In most cases, the semiconductor light source lighting circuit 100 is operated in a situation where the difference between the magnitude of the drive current ILED and the target value is relatively small. When the frequency of the control clock signal S3 and the drive frequency f2 remain independent of each other during such a steady operation, there is a possibility that the oscillation of the drive current ILED occurs depending on the setting of the drive frequency f2. Therefore, the semiconductor light source lighting circuit 100 according to the exemplary embodiment determines the speed of the counting operation of the up/down counter 118 during the steady operation in accordance with the drive frequency f2. By doing so, it is possible to suppress the oscillation of the drive current ILED during the steady operation.
The external variable resistor 60 which has a resistance value giving a desired drive frequency f2 is connected to the external resistor terminal 100a by a user. Here, in the semiconductor light source lighting circuit 100 according to the exemplary embodiment, the switching of the frequency of the control clock signal S3 by the drive frequency f2 is automatically performed by the discrimination circuit 160 and the switching circuit 180. Accordingly, it is not necessary for a user to manually designate the frequency of the control clock signal S3 during the steady operation. As a result, it is not necessary to further provide a terminal for inputting a signal corresponding to such a designation in the control circuit 102 and therefore it is possible to reduce the number of terminals in the control circuit 102.
a) and (b) are waveform diagrams showing a waveform of the drive current ILED during the steady operation. In both
b) corresponds to a case where the speed of the counting operation of the up/down counter 118 is determined in accordance with the drive frequency f2. Particularly in
a) and (b) are waveform diagrams showing a waveform of the drive current ILED when the input voltage Vin is suddenly varied. The frequency of the control clock signal S3 is shown in Table 1. The drive frequency f2 is set to 200 kHz. The reason is that there is a possibility that a light-emitting performance of the LED 40 at the time of the sudden change of the input voltage Vin is deteriorated as the drive frequency f2 becomes lower.
Hereinabove, the configuration and operation of the semiconductor light source lighting circuit according to the exemplary embodiment has been described. The exemplary embodiment is merely an example and it is to be understood by those skilled in the art that the combinations of each component or process can be variously modified and that such modifications fall within the scope of the invention.
Although the control circuit 102 including the drive oscillator 130 and the control oscillator 140 has been described in the foregoing embodiment, the invention is not limited to this configuration. For example, a single oscillator may be used to generate the clock signal of the up/down counter 118 and the element control signal for driving the switching element 122. In this case, since the frequency of the clock signal of the up/down counter 118 is varied in accordance with the frequency of the element control signal, it is possible to suppress the oscillation of the drive current.
Any combinations of the above-described components and optional modifications in the method, apparatus and system are also effective as aspects of the invention.
In accordance with embodiments, a semiconductor light source lighting circuit 100 may include: a switching regulator 104 that generates a drive current ILED of a semiconductor light source 40 using a switching element 122; and a control circuit 102 that controls ON/OFF of the switching element 122 so that the drive current ILED approximates to a target value. The control circuit 102 may include: a comparator 116 that compares the drive current ILED and the target value; an up/down counter 118 that counts a digital value in a count direction determined by a comparison result of the comparator 116; a digital-analog converter 120 that converts the digital value counted by the up/down counter 118 into an analog signal; and a drive circuit 106 that controls the ON/OFF of the switching element 112 based on the analog signal which is obtained as a result of the conversion by the digital-analog converter 120. The up/down counter 118 may count the digital value at a speed determined by an ON/OFF cycle of the switching element 122.
According to this structure, the counting speed of the up/down counter for counting the digital value depends on an ON/OFF cycle of the switching element.
According to this structure, it is possible to suppress an oscillation of the drive current even when the control circuit of the semiconductor light source lighting circuit is digitized.
According to embodiments, the drive circuit 106 may control the ON/OFF of the switching element 122 based on a signal outputted from a first oscillator 130. The up/down counter 118 may perform a counting operation based on a signal outputted from a second oscillator 140 different from the first oscillator 140 when the difference between the drive current ILED and the target value is greater than a current threshold. When the difference between the drive current ILED and the target value is greater than the current threshold, the up/down counter 118 may count the digital value faster than a case when the difference between the drive current ILED and the target value is smaller than the current threshold.
According to embodiments, the up/down counter 118 may count the digital value faster as the ON/OFF cycle of the switching element 122 is shorter.
According to embodiments, the semiconductor light source lighting circuit 100 may include a discrimination circuit 160 that discriminates a magnitude relation between the ON/OFF cycle of the switching element 122 and a cycle threshold, and a determination circuit 180 that determines a counting speed of the up/down counter 118 based on the discrimination result of the discrimination circuit 160.
In accordance with embodiments, a method of lighting a semiconductor light source 40 may include steps of: generating a drive current ILED of the semiconductor light source 40 using a switching element 122; comparing a drive current ILED and a target value by a comparator 116; counting a digital value in a count direction determined by a comparison result of the comparator 116; converting the digital value into an analog signal; and controlling ON/OFF of the switching element 112 based on the analog signal so that the drive current ILED approximates to the target value. The digital value may be counted at a speed determined by an ON/OFF cycle of the switching element 122.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2012-096410 | Apr 2012 | JP | national |
