Claims
- 1. A semiconductor memory comprising:
- capacitors formed at a main surface of a semiconductor substrate for storing information;
- insulated-gate field effect transistors formed at said main surface of the substrate for reading out the signal charges stored in said capacitors;
- word lines for applying signals to a gate electrode of the insulated-gate field effect transistors; and
- data lines for reading out the information stored in said capacitors,
- wherein the capacitors each include an electrode, the electrode having a first side wall and a second side wall, the first and second side walls being formed substantially vertical to the main surface of the substrate, and the second side wall being surrounded by the first side wall, said capacitor further including a capacitor plate, wherein said capacitor plate is formed adjacent to the first and second side walls and is separated from the first and second side walls by an insulating layer so that said first and second side walls respectively face predetermined portions of the capacitor plate and are respectively separated from said predetermined portions of the capacitor plate by said insulating layer,
- wherein a source or drain of each of said insulated-gate field effect transistors is respectively connected to said electrode,
- wherein a drain or source of each of said insulated-gate field effect transistors is connected to one of said data lines, and
- wherein the gate electrode of each of said insulated-gate field effect transistors is connected to one of said word lines.
- 2. The semiconductor memory according to claim 1, wherein said capacitor plate is made chiefly of highly doped poly-silicon.
- 3. The semiconductor memory according to claim 1, wherein the electrode has a third side wall formed substantially vertical to the main surface of the substrate, and wherein the third side wall is surrounded by the first side wall.
- 4. The semiconductor memory according to claim 1, wherein the first side wall is a side wall of a groove provided in the semiconductor substrate.
- 5. The semiconductor memory according to claim 1, wherein the second side wall is a side wall of a post provided in a groove provided in the semiconductor substrate.
- 6. The semiconductor memory according to claim 3, wherein the third side wall is a side wall of a post provided in a groove provided in the semiconductor substrate.
- 7. The semiconductor memory according to claim 1, wherein the insulating layer includes at least two insulating films comprised of materials selected from a group consisting of SiO.sub.2, Si.sub.3 N.sub.4, Ta.sub.2 O.sub.5, TiO.sub.2 and Nb.sub.2 O.sub.5.
- 8. The semiconductor memory according to claim 7, wherein said capacitor plate is made chiefly of highly doped poly-silicon.
- 9. The semiconductor memory according to claim 4, wherein said capacitor plate is made chiefly of highly doped poly-silicon.
- 10. The semiconductor memory according to claim 1, wherein the insulating layer includes Ta.sub.2 O.sub.5.
- 11. The semiconductor memory according to claim 2, wherein the insulating layer includes Ta.sub.2 O.sub.5.
Priority Claims (1)
| Number |
Date |
Country |
Kind |
| 57-18740 |
Feb 1982 |
JPX |
|
Parent Case Info
This is a divisional of application Ser. No. 093,160, filed Sept. 1, 1987, now abandoned which is a continuation application of Ser. No. 465,341, filed Feb. 9, 1983, now abandoned.
The present invention relates to a semiconductor memory and a method for fabricating the same, and more particularly to a semiconductor memory and a method for fabricating the same, which can increase a memory capacity without increasing the amount of required for forming of the memory space.
Since a 1k-bit dynamic random access memory (hereinafter referred to as a dRAM) was first marketed at the beginning of 1970, a MOS dynamic memories which is one of the types of semiconductor IC memories have been scaled up four times in memory capacity in every approximately every three years. A package for accommodating the memory chip primarily uses a 16-pin dual in-line package (DIP) and a cavity size for accommodating the chip is limited. Thus, the size of the memory chip has been increased only about 1.4 times while the integration density has increased four times. Accordingly, a memory cell area per bit has been significantly reduced as the integration density has been increased. Specifically the memory cell are a per bit has been reduced by a factor of three for the increase of the integration density by a factor of four.
Since a capacitance C of the semiconductor memory is represented by C =.epsilon.A/t (where .epsilon. is a dielectric constant of an insulation film, A is an area of a capacitor electrode and t is a thickness of the insulation film between the capacitor electrodes), if the area A is reduced by a factor of three, the capacitance C is also reduced by a factor of three provided that .epsilon. and t are kept constant. A signal quantity S derived from a memory capacitor is proportional to a charge quantity Q which is the product of the capacitance C and a voltage V. Thus, if A is reduced, Q is reduced proportionally and the signal quantity S is also reduced accordingly.
A signal to noise ratio S/N decreases as S decreases. This will raise a big problem in circuit operation. Accordingly, the decrease of A is usually compensated by the decrease of t. Thus, as the integration density is increased to 4 kb, 16 kb and 64 kb, a thickness of a typical SiO.sub.2 film is reduced to 100 nm, 75 nm and 50 nm respectively.
On the other hand, it has been recently found that a charge of approximately 200 fc (femtocoulomb) at maximum is created in a Si substrate by an .alpha. particle radiated from a radioactive heavy metal (U, Th, etc.) contained in the package and this causes an undesirable noise. Accordingly, it is difficult from a standpoint of stable operation to reduce the signal quantity Q below approximately 200 fc. Accordingly, it has been practiced to further reduce the thickness of the insulation film. As a result, another problem of dielectric breakdown of the insulation film has been raised. An electric field for causing dielectric breakdown in the SiO.sub.2 film which is commonly used as the insulation film of the capacitor is 10.sup.7 V/cm at maximum. Thus, an SiO.sub.2 film having a thickness of 10 nm is essentially permanently broken or degraded by an application of a voltage of 10 volts. For long term reliability, it is important to operate the memory at a voltage which is as much smaller than the maximum breakdown voltage as possible.
FIG. 1 shows a configuration of a one-transistor dynamic memory cell which uses an insulated gate field effect transistor (hereinafter referred to as a MOS transistor). It comprises a capacitor 1 for storing a charge and a switching MOS transistor 2, a drain of the switching MOS transistor 2 is connected to a bit line 3 and a gate thereof is connected to a word line 4.
In operation, a signal charge stored in the capacitor 1 is read out by the switching transistor 2. An actual large-scale integration memory is constructed in a memory array by one of the following two major methods. FIG. 2 shows what is called an open bit line configuration in which bit lines 31 and 32 are arranged on opposite sides of a sense amplifier 5 which differentially senses signals. Only one bit line 31 electrically crosses a word line 41, and the sense amplifier 5 senses a difference between the signals on the bit lines 31 and 32.
FIG. 3 shows what is called a folded bit line configuration in which two bit lines 31 and 32 connected to a sense amplifier 5 are arranged in parallel and a word line 41 crosses to two bit lines 31 and 32.
Preferred embodiments of the present invention to be described later are primarily inplemented in the folded bit line configuration although they may be implemented in the open bit line configuration.
In FIGS. 2 and 3, one of major performance indices of the memory array is C.sub.S /C.sub.D, where C.sub.D is a capacitance of a parasitic capacitance 6 of the bit line 32 and C.sub.S is a capacitance of a capacitor 1-2 of the memory cell. The S/N ratio of the memory array directly corresponds to C.sub.S /C.sub.D. It is thus important to increase the capacitance of the memory cell and reduce the parasitic capacitance C.sub.D of the bit line in order to raise the S/N ratio.
FIG. 4 shows a plan structure of a memory cell of the folded bit line configuration, and FIG. 5 shows a sectional structure thereof taken along a line V--V in FIG. 4. As seen from FIGS. 4 and 5, since a capacitor is formed at a portion in an active region 7 (shown in a dumbbell shape) encircled by a thick field oxidization film 11 which is more than 100 nm thick; the active region 7 is covered by a plate 8. However, the plate 8 is selectively removed (shown at 80 in FIG. 4) at an area at which the switching transistor is formed and at an area of a contact hole 9 through which a bit line 3 is connected to a drain (or source) 15 on a Si substrate. Word lines 4 are deposited on the area 80 and the switching transistor 2 is formed there. In some open bit line memories, the switching transistor 2 has no heavily doped region 15 adjacent to the storage capacitor. The term "transistor" will also include such versions.
The semiconductor memory described above is manufactured in the following manner. For the sake of explanation, the transistor is of n-channel type. If a p-channel type is used, the conductivity types of the Si substrate and the diffusion layer are reversed to those in the n-channel type. A field SiO.sub.2 layer 11 which is approximately 100-1000 nm thick is selectively formed on a p-type Si substrate 10 having a resistivity of approximately 10 .OMEGA.-cm by a so-called LOCOS technique which uses Si.sub.3 N.sub.4 as an anti-oxidization mask. Then, a gate oxide film 12 which of 10-100 nm thick is formed on the Si substrate 10 by thermal oxidization. Then, the plate 8 typically formed of poly-Si doped with phosphorus P or arsenic As is selectively deposited and a surface of the poly-Si plate 8 is oxidized to form a first interlayer oxide film 13. Then, the word lines 4 typically formed of poly-Si, Mo silicide or a refractory metal (Mo or W) are deposited and phosphorus P or arsenic As ions are implanted. Thus, n.sup.+ diffusion regions 15 are formed at areas on which the plate 8 and the word lines 4 are not deposited, to form a source and a drain of the switching MOS transistor 2. Then, a phospho-silicate glass (PSG) 14 is deposited to a thickness of 500-1000 nm by a so-called CVD method which contains phosphorus and the contact hole 9 is formed at the area at which the bit line 3 typically formed of an Al electrode is to be connected to the diffusion layer 15. Then, the bit line 3 is selectively deposited thereon.
In the memory cell thus fabricated, the area 16 of the memory capacitor 1 naturally decreases as the size of the memory cell itself decreases. Thus, unless the thickness of the gate oxide film 12 is reduced, the capacitance C.sub.S is reduced as described above and it raises a big problem in the memory operation.
In order to resolve the above problem, it has been proposed by one of the inventors of the present invention to form a narrow groove in the silicon substrate and to form a memory capacitor on the surface of the groove (Japanese Laid-Open Patent Application 51-130178). Since the proposed memory utilizes the side walls and the bottom surface of the groove as electrode surfaces of the capacitor, it can increase the electrode area much more than the memory shown in FIGS. 4 and 5 without increasing the plan area. However, in order to further increase the integration density of the semiconductor IC, the area occupied by the memory cell must be further reduced.
It is an object of the present invention to provide a semiconductor memory having a reduced occupation area and a method for fabricating the same.
It is another object of the present invention to provide a semiconductor memory having a capacitance of an excellent characteristic and a sufficiently small occupation area, and a method for fabricating the same.
It is a further object of the present invention to provide a semiconductor memory having a sufficiently large capacitance without reducing a thickness of an insulation film, and a method for fabricating the same.
In accordance with an aspect of the present invention, a storage capacitor of the semiconductor memory is formed by utilizing a groove formed in a semiconductor substrate and a memory cell of the semiconductor memory is formed in a highly doped area formed in the semiconductor substrate so that a distance between adjacent capacitors can be reduced.
US Referenced Citations (7)
Non-Patent Literature Citations (1)
| Entry |
| Sze, S. M., Physics of Semiconductor Devices, 2nd Ed., John Wiley, 1981, pp. 496-497. |
Divisions (1)
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Number |
Date |
Country |
| Parent |
93160 |
Sep 1987 |
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Continuations (1)
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Number |
Date |
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| Parent |
465341 |
Feb 1983 |
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Patent Grant
5017981
