Claims
- 1. A semiconductor memory integrated circuit comprising:
- an array of memory cell arrays, said array having digital addresses in a sequence in which addresses of adjacent arrays differ in only one digit,
- a plurality of blocks of sense amplifiers and input/output circuitry disposed between and shared by two adjacent arrays of memory cells, and
- logic circuitry for the selection of each shared sense amplifier and I/O circuitry responsive to common bits of two array select addresses for adjacent arrays wherein each logic circuit responds to all address bits except one of the array select address for the two adjacent arrays.
- 2. The semiconductor memory integrated circuit as defined by claim 1 wherein said logic circuitry comprises an AND function of all bits of the array select address except for the single bit that differs in the address selecting the memory arrays on each side of the sense amplifier and input/output circuitry.
- 3. A method of accessing arrays of memory in a semiconductor memory integrated circuit comprising the steps of:
- a) assigning digital addresses to the arrays of memory in accordance with a data sequence in which addresses of adjacent arrays differ in only one digit,
- b) providing a shared block of sense amplifiers and input/output circuitry between adjacent arrays of memory, and
- c) activating a shared block of sense amplifiers and input/output circuitry with a decoder that is an AND function of all bits of the array select address for each adjacent memory array except for the one digit that differs in the address of the two adjacent memory arrays.
Parent Case Info
This is a continuation of Provisional Application, Ser. No. 60/047,370 filed on Jun. 2, 1997.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4748552 |
Fung et al. |
May 1998 |
|
5586078 |
Takase et al. |
Dec 1996 |
|
5812481 |
Numata et al. |
Sep 1998 |
|