Semiconductor memory cell and array using punch-through to program and read same

Abstract

An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell. In response to the first set of write control signals, the punch-through mode transistor provides at least the first charge in the body region via impact ionization. The transistor may be disposed on a bulk-type substrate or SOI-type substrate.

Description

BACKGROUND

These inventions relates to a semiconductor memory cell, array, architecture and device, and techniques for reading, controlling and/or operating such cell and device; and more particularly, in one aspect, to a semiconductor dynamic random access memory (“DRAM”) cell, array, architecture and/or device wherein the memory cell includes an electrically floating body in which an electrical charge is stored.

One type of dynamic random access memory cell is based on, among other things, a floating body effect of semiconductor on insulator (“SOI”) transistors. (See, for example, U.S. patent application Ser. No. 10/450,238, Fazan et al., filed Jun. 10, 2003 and entitled “Semiconductor Device”, hereinafter “Semiconductor Memory Device Patent Application”). In this regard, the memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation or non-conductive region (for example, in bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge in the body region of the transistor.

With reference to FIGS. 1A, 1B and 1C, in one embodiment, semiconductor DRAM array 10 includes a plurality of memory cells 12, each consisting of transistor 14 having gate 16, an electrically floating body region 18, source region 20 and drain region 22. The body region 18 is disposed between source region 20 and drain region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in SOI material/substrate) or non-conductive region (for example, in bulk-type material/substrate). The insulation or non-conductive region may be disposed on substrate 26.

Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18. Notably, the entire contents of the Semiconductor Memory Device Patent Application, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.

Notably, for at least the purposes of this discussion, logic high or State “1” corresponds to an increased concentration of majority carriers in the body region relative to an unprogrammed device and/or a device that is programmed with a logic low or State “0”. In contrast, a logic low or State “0” corresponds to a reduced concentration of majority carriers in the body region relative to an unprogrammed device and/or a device that is programmed with logic high or State “1”.

SUMMARY OF THE INVENTIONS

There are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein.

In a first principle aspect, the present inventions are directed to an integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including at least one transistor, wherein the transistor, in operation, operates in a punch-through. The transistor includes (i) a first region having impurities to provide a first conductivity type and a first junction, (ii) a second region having impurities to provide a first conductivity type and a second junction, wherein when the transistor is in operation, the first and second junctions abut or overlap, (iii) a body region, disposed between the first region and the second region, having impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type. The transistor further includes (i) a gate disposed over the body region and (ii) a gate insulator disposed between the gate and the body region wherein the body region includes a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of a charge in the body region.

The integrated circuit device further includes first circuitry, coupled to the transistor of the memory cell, to: (1) generate first and second sets of write control signals and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell. In response to the first set of write control signals, the transistor provides at least a first charge (for example, substantially in the storage node of the body region) which is representative of the first data state in the body region via impact ionization.

In one embodiment, the body region of the transistor is electrically floating. In another embodiment, the transistor is disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate wherein the body region is disposed between the first region, the second region, the gate insulator and the insulating region or layer of the substrate. The transistor may be disposed on bulk-type semiconductor substrate or SOI-type substrate.

In one embodiment, the transistor, in response to read control signals applied to the memory cell, generates a punch-through current which is representative of the data state of the memory cell and wherein the data sense circuitry determines the data state of the memory cell at least substantially based on the second bipolar transistor current. The integrated circuit device may further include second circuitry to read the data state of the memory cell wherein second circuitry determines the data state of the memory cell at least substantially based on a punch-through current.

In another principal aspect, the present inventions are directed to an integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including at least one punch-through mode transistor, wherein the punch-through mode transistor includes: (i) a first region, (ii) a second region, (iii) a body region disposed between the first region and the second region, (iv) a gate disposed over the body region and (v) a gate insulator disposed between the gate and the body region wherein the body region includes a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states including (i) a first data state which is representative of a first charge in the body region, and (ii) a second data state which is representative of a second charge in the body region.

The integrated circuit device of this aspect may include first circuitry, coupled to the transistor of the memory cell, to: (1) generate first and second sets of write control signals and (2a) apply the first set of write control signals to the transistor to write the first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write the second data state in the memory cell. The transistor, in response to the first set of write control signals, stores at least the first charge in the body region (for example, substantially in the storage node) wherein the first charge is provided or created via impact ionization and, in response to the second set of write control signals, the transistor stores no more than the second charge in the body region.

In one embodiment, the body region of the transistor is electrically floating. In another embodiment, the transistor is disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate wherein the body region is disposed between the first region, the second region, the gate insulator and the insulating region or layer of the substrate. The transistor may be disposed on bulk-type semiconductor substrate or SOI-type substrate.

In one embodiment, the transistor, in response to read control signals applied to the memory cell, generates a punch-through current which is representative of the data state of the memory cell and wherein the data sense circuitry determines the data state of the memory cell at least substantially based on the second bipolar transistor current. The integrated circuit device may further include second circuitry to read the data state of the memory cell wherein second circuitry determines the data state of the memory cell at least substantially based on a punch-through current.

Notably, the second charge may be provided in the body region by causing majority carriers out of the body region via the first and/or second regions.

In another principal aspect, the present inventions are directed to an integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including at least one punch-through mode transistor, wherein the punch-through mode transistor includes: (i) a first region, (ii) a second region, (iii) a body region disposed between the first region and the second region, (iv) a gate disposed over the body region and (v) a gate insulator disposed between the gate and the body region wherein the body region includes a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the body region.

The integrated circuit device of this aspect further includes first circuitry, coupled to the punch-through mode transistor of the memory cell, to: (1) generate first and second sets of write control signals and (2a) apply the first set of write control signals to the punch-through mode transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the punch-through mode transistor to write a second data state in the memory cell. In response to the first set of write control signals, the punch-through mode transistor stores a charge in the body region (for example, substantially in the storage node of the body region) which is provided or created via impact ionization.

In one embodiment, the body region of the transistor is electrically floating. In another embodiment, the transistor is disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate wherein the body region is disposed between the first region, the second region, the gate insulator and the insulating region or layer of the substrate. The transistor may be disposed on bulk-type semiconductor substrate or SOI-type substrate.

In one embodiment, the transistor, in response to read control signals applied to the memory cell, generates a punch-through current which is representative of the data state of the memory cell and wherein the data sense circuitry determines the data state of the memory cell at least substantially based on the second bipolar transistor current. The integrated circuit device may further include second circuitry to read the data state of the memory cell wherein second circuitry determines the data state of the memory cell at least substantially based on a punch-through current.

In another principal aspect, the present inventions are directed to an integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including at least one transistor, wherein the transistor, in operation, operates in a punch-through. The transistor includes: (i) a first region having impurities to provide a first conductivity type and a first junction, (ii) a second region having impurities to provide a first conductivity type and a second junction, wherein when the transistor is in operation, the first and second junctions abut or overlap, (iii) a body region, disposed between the first region and the second region, having impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type, (iv) a gate disposed over the body region, and (v) a gate insulator disposed between the gate and the body region wherein the body region includes a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region.

The integrated circuit device of this aspect of the present inventions further includes first circuitry, coupled to the transistor of the memory cell, to: (1) generate first and second sets of write control signals and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell. In response to the first set of write control signals, the transistor stores a charge in the body region (for example, substantially in the storage node of the body region) which is provided or created via impact ionization.

In one embodiment, the body region of the transistor is electrically floating. In another embodiment, the transistor is disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate wherein the body region is disposed between the first region, the second region, the gate insulator and the insulating region or layer of the substrate. The transistor may be disposed on bulk-type semiconductor substrate or SOI-type substrate.

In one embodiment, the transistor, in response to read control signals applied to the memory cell, generates a punch-through current which is representative of the data state of the memory cell and wherein the data sense circuitry determines the data state of the memory cell at least substantially based on the second bipolar transistor current. The integrated circuit device may further include second circuitry to read the data state of the memory cell wherein second circuitry determines the data state of the memory cell at least substantially based on a punch-through current.

Again, there are many inventions, and aspects of the inventions, described and illustrated herein. This Summary of the Inventions is not exhaustive of the scope of the present inventions. Moreover, this Summary of the Inventions is not intended to be limiting of the inventions or the claims (whether the currently presented claims or claims of a divisional/continuation application) and should not be interpreted in that manner. While certain embodiments have been described and/or outlined in this Summary of the Inventions, it should be understood that the present inventions are not limited to such embodiments, description and/or outline, nor are the claims limited in such a manner (which should also not be interpreted as being limited by the Summary of the Inventions).

Indeed, many other aspects, inventions and embodiments, which may be different from and/or similar to, the aspects, inventions and embodiments presented in this Summary, will be apparent from the description, illustrations and claims, which follow. In addition, although various features, attributes and advantages have been described in this Summary of the Inventions and/or are apparent in light thereof, it should be understood that such features, attributes and advantages are not required whether in one, some or all of the embodiments of the present inventions and, indeed, need not be present in any of the embodiments of the present inventions.

BRIEF DESCRIPTION OF THE DRAWINGS

In the course of the detailed description to follow, reference will be made to the attached drawings. These drawings show different aspects of the present inventions and, where appropriate, reference numerals illustrating like structures, components, materials and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, materials and/or elements, other than those specifically shown, are contemplated and are within the scope of the present inventions.

Moreover, there are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein.

FIG. 1A is a schematic representation of a prior art DRAM array including a plurality of memory cells, each having one electrically floating body transistor;

FIG. 1B is a three-dimensional view of an exemplary prior art memory cell comprised of one electrically floating body partially depleted transistor (PD-SOI NMOS);

FIG. 1C is a cross-sectional view of the prior art memory cell of FIG. 1B, cross-sectioned along line C-C′;

FIGS. 2A and 2B are exemplary cross-sectional illustrations of a memory cell using SOI and bulk semiconductor technologies, respectively, according to exemplary embodiments of the present inventions;

FIGS. 3A and 3B are exemplary cross-sectional illustrations of a memory cell according to the present inventions, in conjunction with exemplary control voltages applied to various regions or portions of the memory cell to program the memory cell to logic state “1” (i.e., generate or provide an excess of majority carrier in the electrically floating body of the memory cell of FIGS. 2A and 2B); notably, majority carriers in these exemplary embodiments are generated or provided (or substantially generated or provided) via punch-through electron impact ionization;

FIGS. 4A and 4B are exemplary cross-sectional illustrations of a memory cell according to the present inventions, in conjunction with exemplary control voltages applied to various regions or portions of the memory cell to program the memory cell to logic state “0” (i.e., provide relatively fewer majority carrier by removing from the electrically floating body region of the transistor of the memory cell of FIGS. 2A and 2B); notably, majority carriers may be removed through the drain region/terminal and/or the source region/terminal, and/or through both drain and source regions/terminals and/or punch-through area via application of control signals applied to the various regions or portions of the memory cell, for example, via application of a gate voltage/bias (i.e., voltage applied to the gate), which is higher than the holding gate voltage/bias, and a drain voltage/bias, which is lower than the voltage applied to the drain when writing logic state “1” (i.e., the drain voltage/bias for logic state “1”);

FIGS. 5A and 5B are exemplary cross-sectional illustrations of a memory cell according to the present inventions, in conjunction with exemplary control voltages applied to various regions or portions of the memory cell to read the stored data state (i.e., sense the data state stored in the memory cell—that is, the charge carrier concentration in the electrically floating body region of the transistor which is representative of a predetermined data state of the memory cell of FIGS. 2A and 2B); notably, in an exemplary embodiment, the data state of the memory cell may be determined by sensing or sampling the amount of the punch-through current provided/generated (or substantially provided/generated) in response to the application of a predetermined voltages on the gate and drain of the transistor of the memory cell using, for example, a sense amplifier;

FIG. 6A illustrates exemplary timing relationships and control signal waveform of (i) selected write control signals for programming or writing a logic state “0” into one or more N-channel type memory cells, (ii) programming or writing logic state “1” into one or more N-channel type memory cells, and (iii) reading one or more N-channel type memory cells, according to an exemplary embodiment of the present inventions;

FIG. 6B illustrates exemplary timing relationships and control signal waveform of (i) selected write control signals for programming or writing a logic state “0” into one or more N-channel type memory cells, (ii) programming or writing logic state “1” into one or more N-channel type memory cells, and (iii) reading one or more N-channel type memory cells, according to an exemplary embodiment of the present inventions;

FIGS. 7 and 8 illustrate exemplary embodiments of a memory array having a plurality of memory cells and employing a separated source line configuration for each row of memory cells, in conjunction with exemplary programming techniques, including exemplary control signal voltage values (FIG. 7) and exemplary reading techniques, including exemplary control signal voltage values (FIG. 8), according to certain aspects of the present inventions;

FIGS. 9 and 10 illustrate exemplary embodiments of a memory array having a plurality of memory cells and employing a common source line configuration for each row of memory cells in conjunction with exemplary programming techniques, including exemplary control signal voltage values (FIG. 9), and exemplary reading techniques, including exemplary control signal voltage values (FIG. 10), according to certain aspects of the present inventions;

FIG. 11 illustrates non-disturbing reading of the proposed memory cell according to an exemplary embodiment of the present inventions; and

FIGS. 12A-12C are schematic block diagram illustrations of exemplary integrated circuit devices in which the memory cell array (and certain peripheral circuitry) may be implemented, according to one or more aspects of the present inventions.

DETAILED DESCRIPTION

In one aspect, the present inventions are directed to techniques for reading, controlling and/or operating a semiconductor memory cell, array, and device having memory cells including at least one electrically floating body transistor in which electrical charge is stored in the body of the transistor. The present inventions are also directed to semiconductor memory cell, array, architecture and device that include circuitry to implement such reading, controlling and/or operating techniques. The memory cell array may comprise a portion of an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory device) having a plurality of memory cells. The inventive programming techniques may be implemented with or without employing a back gate or substrate terminals for SOI and bulk semiconductor technologies.

Further, the present inventions, in one aspect, describe a new memory cell and a combination of the programming/reading methods. The memory cell may be implemented in a memory array which is disposed in/on a logic or discrete memory device. Such logic or discrete memory device may be smaller and consume less power in view of memory cells array implementing conventional architectures and techniques. Notably, the present inventions may be implemented on or in an SOI technology or a bulk semiconductor technology and may provide a memory cell comprising an electrically floating body transistor that is less sensitive to technology variations having improvement in retention characteristics relative to conventional architectures and techniques.

With reference to FIGS. 2A and 2B, in a first set of embodiments, the present inventions employ memory cell 12 including transistor 14, having a body region, which is disposed on or in an SOI technology (FIG. 2A) or a bulk semiconductor technology (FIG. 2B). The transistor 14 is configured, controlled and/or designed to operate in a punch-through mode. In this embodiment, the junctions (or the depletion regions) between (i) source region 20 and body region 18 and (ii) drain region 22 and body region 18 abut or overlap.

In the illustrated exemplary embodiments, the “punch-through” transistor 14 is depicted as an N-channel type device. As such, majority carriers 34 are “holes”. The “punch-through” transistor may also be a P-channel type device. Under these circumstances, the majority carriers are electrons.

The portion of the body region which is located immediately under gate 16 and/or gate oxide 32 forms at least a portion (for example, a substantial portion) of the storage node of memory cell 12. In this regard, the portion of the body region which is located immediately under gate 16 and/or gate oxide 32 is (sufficiently) electrically isolated from other portions of the body region of transistor 14 by the punch-through configuration.

Notably, with reference to FIG. 3A, in case of an SOI technology, a portion of the charge may be stored in the area close to the interface of insulation region 24 (for example, a buried silicon dioxide or other insulator). Moreover, with reference to FIG. 2B, the portion of the body region which is located immediately under gate 16 and/or gate oxide 32 is (sufficiently) electrically isolated from other portions of the body region of transistor 14 as well as portions of the substrate which are beneath the source, drain and body regions. The punch-through transistor may be “optimized” and/or enhanced for the type of memory cell by adjusting the gate length, body doping and source/drain junctions.

In operation, when writing or programming a logic “1” or logic high, in one exemplary embodiment, control signals (having exemplary voltages of: Vg=−1.2V, Vd=+2V and Vs=0V) are applied to gate 16, source region 20 and drain region 22 (respectively) of transistor 14 of memory cell 12 which, in combination, induce, cause, provide and/or result in impact ionization via the punch-through current (see, FIGS. 3A and 3B). In another embodiment, when writing or programming a logic “1” or logic high, control signals (having exemplary voltages of: Vg=−2.5V, Vd=+2.5V and Vs=0V) are applied to gate 16, source region 20 and drain region 22 (respectively) of transistor 14 of memory cell 12 which, in combination, induce, cause, provide and/or result in generation of majority carriers by the GIDL (band-to-band tunneling). The generated majority carriers are, at least in part, stored in a portion of the body region that is located immediately under gate 16 and/or gate oxide 32 (FIGS. 3A and 3B). As noted above, in case of an SOI technology, a portion of the charge may be stored in the area close to the interface of insulation region 24 (for example, a buried silicon dioxide or other insulator) (see, FIG. 3A).

Where the memory cell of the present inventions is implemented in a memory array, it may be advantageous to implement a “holding” operation when programming one or more of the memory cells of the array to enhance the retention characteristics of the memory cell. The transistor 14 of memory cell 12 may be placed in a “holding” state via application of control signals that are applied to gate 16 and source region 20 and drain region 22 of transistor 14 of memory cell 12. In combination, such control signals provide, cause and/or induce majority carrier accumulation in an area that is located immediately under gate 16 and/or gate oxide 32. In this embodiment, it may be preferable to apply a negative voltage to gate 16 where transistor 14 is an N-channel device. Holding voltages may be optimized to obtain a suitable, enhanced and/or maximum retention time. For example, in one exemplary embodiment, control voltages to establish the “holding” state include: Vg=−1.2V, Vs=Vd=0V.

Further, when writing or programming a logic “0” in transistor 14 of memory cell 12, in one exemplary embodiment, the control signals (having exemplary voltages of: Vg=0.5v, Vd=2v and Vs=0v) may be applied to gate 16, source 18 and drain 20 of transistor 14 such that, in at least one embodiment, the voltage applied to gate 16 of transistor 14 of memory cell 12 is higher than a holding voltage (if applicable)). In response, majority carriers are removed from the body region of transistor 14. For example, in one embodiment, the majority carriers may be removed, eliminated and/or ejected from the body region of transistor 14 through (i) source region 20, (ii) drain region, or (iii) source region 20 and drain region 22. In another example, the majority carriers may be removed, eliminated and/or ejected from the body region via punch-through. (See, FIGS. 4A and 4B).

With reference to FIGS. 5A and 5B, in another set of embodiments, the data state of memory cell 12 may be sensed, sampled, read and/or determined by applying control signals (having exemplary voltages of: Vg=−0.8v, Vd=0.5v and Vs=0v) to gate 16 and source region 20 and drain region 22 of transistor 14. Such signals, in combination, induce and/or cause a punch-through current. The amount of the punch-through current is, at least in part, determined or defined by the amount of charge stored in transistor 14. As such, the data state of memory cell 12 may be determined by sensing, sampling, reading and/or determining the punch-through current using data sense circuitry, for example, sense amplifier circuitry (such as a cross-coupled sense amplifier).

With reference to FIGS. 6A, 6B, 7 and 9, in exemplary embodiments, control signals having a predetermined amplitude may be selectively applied to a row of memory cells (for example, memory cells 12a-d, which are coupled to word lines 28_i) to write logic state “1” into selected memory cells 12a and 12d, and logic state “0” into selected memory cells 12b and 12c. In particular, in this exemplary embodiment, a logic state “1” may be programmed or written in memory cells 12a and 12d by applying a voltage pulse of +2V to source region 20 of the transistors of memory cells 12a and 12d and a voltage pulse of +0.5V to gate 16 of the transistors of memory cells 12a and 12d. The source pulse may be applied before the gate pulse, simultaneously thereto, or after the gate pulse is applied to gate 16 of the transistors of memory cells 12a and 12d. It is preferred that the source pulse be applied to source region 20 of the transistors of memory cells 12a and 12d with a sufficient amplitude to maintain a sufficient punch-through current to program a logic state “1” into memory cells 12a and 12d. From a relative timing perspective, it is preferred that the source pulse extends beyond when the gate pulse reduces or ceases. (See, for example, FIGS. 6A and 6B).

With continued reference to FIGS. 6A, 6B, 7 and 9, in these exemplary embodiments, control signals having predetermined amplitudes may be applied to the transistors of memory cells 12b and 12c to write or program logic state “0” therein. The source pulse may be applied to source region 20 of the transistors of memory cells 12b and 12c before the gate pulse is applied to gate 16 of the transistors of memory cells 12b and 12c, or simultaneously thereto, or after the gate pulse is applied to gate 16 of the transistors of memory cells 12b and 12c. Further, as illustrated, a drain pulse (0.5V amplitude in this example) is applied to drain regions 22 of the transistors of memory cells 12b and 12d to prevent, prohibit, limit and/or retard a punch-through current from causing or generating a sufficient charge in the floating body region of memory cells 12b and 12c to program or write a logic state “1” into memory cells 12b and 12c. The drain pulse may be characterized as a “blocking” pulse.

Again, from a relative timing perspective, it is preferred that the drain pulse be applied to drain region 22 of the transistors of memory cells 12b and 12c for a temporal period that is applied before, during and after the source and gate pulses, for example, initiates, starts, ramps, declines and/or terminates), (See, for example, FIGS. 6A and 6B).

Notably, with continued reference to FIGS. 6A, 6B, 7 and 9, for those unselected memory cells (i.e., the memory cells coupled to word lines 28_i+1, 28_i+2, 28_i+2 and 28_i+4), a holding condition may be applied or established to prevent, minimize and/or avoid disturbance of the data state of, or charge stored in the unselected memory cells. In this regard, a voltage (for example, −1.2V) may be applied to gates 16 of the transistors of the unselected memory cells and a voltage (for example, 0V) may be applied to source regions 20 and drain regions 22 of the transistors of the unselected memory cells to prevent, minimize or avoid disturbance of the data state in the unselected memory cells during the programming or writing operation. Under these conditions, the data state of the unselected memory cells may be unaffected (or substantially unaffected) by the programming of or writing to selected memory cells 12a-12d.

With reference to FIGS. 6A, 6B, 8 and 10, in the illustrated exemplary embodiments, control signals having a predetermined amplitude may be selectively applied to a row of memory cells (for example, memory cells 12a-12d which are coupled to word lines 28_i) to read the data state in each of the selected memory cells 12a-12d. For example, a voltage pulse of +0.5V may be applied to source region 20, and a voltage pulse of −0.8V may be applied to gate 16 of the transistors of memory cells 12a-12d. In this embodiment, the source pulse may be applied to source region 20 before application of the gate pulse to gate 16, simultaneously thereto, or after the gate pulse is applied to gate 16 of the transistors of memory cells 12a-12d. Further, the source pulse may cease or terminate before the gate pulse, simultaneously thereto (as illustrated in FIGS. 6A and 6B), or after the gate pulse concludes or ceases.

Notably, for those memory cells that are not read (i.e., those memory cells coupled to word lines 28_i+1, 28_i+2, 28_i+3 and 28_i+4), a holding condition may be applied or established to prevent, minimize and/or avoid disturbance of the data state in the unselected memory cells. In this regard, a voltage (for example, −1.2V) may be applied to gates 16 of the transistors of the unselected memory cells and a voltage (for example, 0V) may be applied to source regions 20 of the transistors of the unselected memory cells to prevent, minimize or avoid disturbance of the data state in the unselected memory cells during the read operation. Under these conditions, the state of the unselected memory cells may be unaffected (or substantially unaffected) during the reading of selected memory cells 12a-12d.

With reference to FIG. 11, in an exemplary embodiment, reading may be performed many times in sequence without losing a detrimental amount of charge stored in the body region of the transistor. In this way, the memory cell may undergo multiple read operations without the loss of an amount of charge that would result in destruction of the data state (i.e., the data state of the memory cell being undeterminable by sensing circuitry, for example, a sense amplifier).

The illustrated/exemplary voltage levels to implement the write and read operations are merely exemplary. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.25, 0.5, 1.0 and 2.0 volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative.

Notably, the reading technique described herein may reduce the degradation of the charge in the electrically floating body which results from or is caused by charge-pumping (charge-pumping disturb). In this way, the memory cell provides a quasi non-disturbing reading. Thus, when memory cell 12 is read multiple times without or before a refresh operation, the read window remains relatively stable for each successive read operation. (See, for example, FIG. 11).

The memory cells of the memory array(s) may be comprised of N-channel, P-channel and/or both types of transistors. Further, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include P-channel and/or N-channel type transistors. Where P-channel type transistors are employed as memory cells 12 in the memory array(s), suitable write and read voltages (for example, negative voltages) are well known to those skilled in the art in light of this disclosure.

A memory cell which is includes an electrically floating body transistor, which state is read/programmed using the techniques of the present invention, may be employed in any array, architecture, layout, structure and/or configuration employing such memory cells. In this regard, an electrically floating body transistor, which state is programmed and/or read using the techniques of the present invention, may be implemented in the memory cell, architecture, layout, structure and/or configuration described and illustrated in the following non-provisional U.S. patent applications:

(1) U.S. Non-Provisional patent application Ser. No. 10/450,238, which was filed by Fazan et al. on Jun. 10, 2003 and entitled “Semiconductor Device” (now U.S. Pat. No. 6,969,662);

(2) U.S. Non-Provisional patent application Ser. No. 10/487,157, which was filed by Fazan et al. on Feb. 18, 2004 and entitled “Semiconductor Device” (now U.S. Pat. No. 7,061,050);

(3) U.S. Non-Provisional patent application Ser. No. 10/829,877, which was filed by Ferrant et al. on Apr. 22, 2004 and entitled “Semiconductor Memory Cell, Array, Architecture and Device, and Method of Operating Same” (now U.S. Pat. No. 7,085,153);

(4) U.S. Non-Provisional patent application Ser. No. 11/096,970, which was filed by Ferrant et al. and entitled “Semiconductor Memory Device and Method of Operating Same” (now U.S. Pat. No. 7,085,156);

(5) U.S. Non-Provisional patent application Ser. No. 10/941,692, which was filed by Fazan et al. on Sep. 15, 2004 and entitled “Low Power Programming Technique for a One Transistor SOI Memory Device & Asymmetrical Electrically Floating Body Memory Device, and Method of Manufacturing Same” (now U.S. Pat. No. 7,184,298);

The entire contents of these five (5) U.S. patent applications, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein. For the sake of brevity, those discussions will not be repeated; rather those discussions (text and illustrations), including the discussions relating to the memory cell, architecture, layout, structure, are incorporated by reference herein in its entirety.

Indeed, the memory cells of the present inventions may be implemented in any memory array having, for example, a plurality of rows and columns (for example, in a matrix form). Moreover, the present inventions may be implemented in any memory cell and/or memory cell array having an electrically floating body transistor. For example, the present inventions may be employed in a memory array, having a plurality of memory cells each including an electrically floating body transistor wherein such memory cells are written, controlled, programmed and/or read according to any of the techniques described and/or illustrated herein. The data states of adjacent memory cells and/or memory cells that share a word line may be individually and selectively programmed.

There are many inventions described and illustrated herein. While certain embodiments, features, attributes and advantages of the inventions have been described and illustrated, it should be understood that many others, as well as different and/or similar embodiments, features, attributes and advantages of the present inventions, are apparent from the description and illustrations. As such, the embodiments, features, attributes and advantages of the inventions described and illustrated herein are not exhaustive and it should be understood that such other, similar, as well as different, embodiments, features, attributes and advantages of the present inventions are within the scope of the present inventions. Indeed, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein.

For example, memory cells having P-type or N-type transistors (whether symmetrical or non-symmetrical and/or whether disposed on/in a bulk semiconductor material or an SOI material) may be employed in any of the embodiments described and/or illustrated herein. Indeed, all permutations and combinations of the memory cells with such embodiments and/or features thereof, are intended to come within the scope of the present inventions. For the sake of brevity, such permutations and combinations are not discussed in detail herein.

Notably, where the memory cells include at least one electrically floating body transistor to store a charge in the electrically floating body region, such transistors may be symmetrical or non-symmetrical. Where the transistor are symmetrical, the source and drain regions are essentially interchangeable. However, where the transistor are non-symmetrical device, the source or drain regions of transistors have different electrical, physical, doping concentration and/or doping profile characteristics. As such, the source or drain regions of a non-symmetrical device are typically not interchangeable. This notwithstanding, the drain region of the electrically floating N-channel type transistor of the memory cell (whether the source and drain regions are interchangeable or not) is that region of the transistor that is connected to the bit line/sense amplifier.

As mentioned above, the inventions (and embodiments thereof) described and illustrated herein are entirely applicable to N-channel and/or P-channel type transistors. Moreover, while the discussion described and illustrated only source and drain implants, other implants may also be included. For example, implants to modify the operation of memory cells 12, which affect, for example, the power consumption of memory cells 12 as described and illustrated in (1) U.S. Pat. No. 6,969,662 (identified above), (2) U.S. Pat. No. 7,061,050 (identified above), and (3) Provisional Application Ser. No. 60/578,631, which was filed on Jun. 10, 2004 and entitled “Asymmetrical Electrically Floating Body Memory Device, and Method of Manufacturing Same”.

Further, as mentioned above, the memory arrays may be comprised of N-channel type transistors, P-channel type transistors and/or both types of transistors, as well as partially depleted and/or fully depleted type transistors. For example, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include fully depleted type transistors (whether P-channel and/or N-channel type). Alternatively, such circuitry may include partially depleted type transistors (whether P-channel and/or N-channel type). There are many techniques to integrate both partially depleted and/or fully depleted type transistors on the same substrate (see, for example, U.S. Pat. No. 7,061,050). All such techniques, whether now known or later developed, are intended to fall within the scope of the present inventions.

Notably, memory cell selection circuitry may employ any circuitry and/or technique now known or later developed to select one or more memory cells for reading and/or programming. Indeed, all such techniques and circuitry therefor, whether now known or later developed, are intended to fall within the scope of the present inventions.

Further, data write and sense circuitry may employ any circuitry whether now known or later developed. For example, the data write and sense circuitry may employ a sense amplifier to read the data stored in memory cells 12. The sense amplifier may sense the data state stored in memory cell 12 using voltage or current sensing techniques. In the context of a current sense amplifier (for example, Non-Provisional U.S. patent application Ser. No. 11/299,590 (U.S. Patent Application Publication US 2006/0126374), filed by Waller and Carman, on Dec. 12, 2005 and entitled “Sense Amplifier Circuitry and Architecture to Write Data into and/or Read Data from Memory Cells”, the sense amplifier may compare the memory cell current to a reference current, for example, the current of a reference cell. From that comparison, the data state of memory cell 12 may be determined (for example, whether the memory cell 12 contained a logic high (relatively more majority carries 34 contained within body region 18) or logic low data state (relatively less majority carries 34 contained within body region 18)).

The reference current or voltage may be substantially equal to one-half of the summation of the currents in a first reference cell, which has a logic low data state, and a second reference cell, which has a logic high data state. Other reference current or voltage levels are suitable. Moreover, a reference generator circuitry is described in the context of generating, providing and/or supplying a reference current or voltage. The circuitry and techniques described and illustrated in U.S. patent application Ser. No. 10/840,902, which was filed by Portmann et al. on May 7, 2004, and entitled “Reference Current Generator, and Method of Programming, Adjusting and/or Operating Same” (now U.S. Pat. No. 6,912,150), may be employed to generate an appropriate reference current for the data write and sense circuitry. The entire contents of U.S. patent application Ser. No. 10/840,902, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein.

In addition, the circuitry and techniques described and illustrated in U.S. patent application Ser. No. 11/515,667 (U.S. Patent Application Publication US 2007/0064489), which was filed by Bauser on Sep. 5, 2006, and entitled “Method and Circuitry to Generate a Reference Current for Reading a Memory Cell, and Device Implementing Same”, may be employed to generate an appropriate reference current for the data write and sense circuitry. The entire contents of U.S. patent application Ser. No. 11/515,667, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein. Notably, all such techniques and circuitry to generate an appropriate reference current for the data write and sense circuitry, whether now known or later developed, are intended to fall within the scope of the present inventions.

Further, although the present inventions have been described in the exemplary embodiments as a single-bit memory cell, the present inventions may be implemented in memory cells that store more than one bit of data. For example, the present inventions may be implemented in conjunction with the inventions, embodiments, memory cells, memory cell arrays and architectures described and/or illustrated in U.S. Non-Provisional patent application Ser. No. 11/703,429, which was filed by Okhonin et al, on Feb. 7, 2007, and entitled “Multi-Bit Memory Cell Having Electrically Floating Body Transistor, and Method of Programming and Reading Same”. In this regard, the multi-bit memory cell, and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) may be programmed using the techniques described and illustrated herein. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc.) and/or more than two data states (for example, three, four, five, six, etc. data or logic states).

An analog-to-digital converter circuitry and/or one or more sense amplifiers (not illustrated) may be employed to read the multi-bit data stored in a memory cell (having an electrically floating body transistor). The sense amplifier may sense the data state stored in the memory cell using voltage or current sensing techniques. In the context of a current sense amplifier, the current sense amplifier may compare the cell current to one or more reference currents, for example, the current of a reference cell (not illustrated). From that comparison, the data state of the memory cell may be determined (which is indicative of the number of majority carriers contained within electrically floating body region of the transistor).

Further, the present inventions may employ the circuitry and techniques for independently controlling certain parameters (for example, temporal or voltage), for a memory operation (for example, restore, write, refresh), to program or write a predetermined data state into a memory cell (for example, programming or writing data state “1” or “0” into a memory cell) as described and illustrated in U.S. patent application Ser. No. 11/590,147, which was filed by Popoff et al. on Oct. 31, 2006, and entitled “Method and Apparatus for Varying the Programming Duration and/or Voltage of an Electrically Floating Body Transistor, and Memory Cell Array Implementing Same”. For example, the duration of programming/writing/refreshing of a given memory state into a memory cell by data write and sense circuitry may be controlled, adjusted, determined and/or predetermined according to or based on the given memory operation (for example, restore, write, refresh). Likewise, the voltage conditions applied to the memory cell for programming/writing a given memory state into a memory cell by data write and sense circuitry may be controlled and/or adjusted according to the memory operation (for example, restore, write, refresh). The entire contents of U.S. patent application Ser. No. 11/590,147, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein.

The transistors, memory cells and arrays may be fabricated using well known techniques and/or materials. Indeed, any fabrication technique and/or material, whether now known or later developed, may be employed to fabricate the memory cells, transistors and/or memory array(s). For example, the present inventions may employ silicon (whether bulk-type or SOI), germanium, silicon/germanium, gallium arsenide or any other semiconductor material in which transistors may be formed. Indeed, the electrically floating body transistors, memory cells, and/or memory array(s) may employ the techniques described and illustrated in non-provisional patent application entitled “Integrated Circuit Device, and Method of Fabricating Same”, which was filed on Jul. 2, 2004, by Fazan, Ser. No. 10/884,481 (U.S. Patent Application Publication US 2005/0017240) and/or non-provisional patent application entitled “One Transistor Memory Cell having a Strained Electrically Floating Body Region, and Method of Operating Same”, which was filed on Oct. 12, 2006, and assigned Ser. No. 11/580,169, by Bassin (hereinafter collectively “Integrated Circuit Device Patent Applications”). The entire contents of the Integrated Circuit Device Patent Applications, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein.

Indeed, the memory array (including, for example, SOI memory transistors) may be integrated with SOI logic transistors, as described and illustrated in the Integrated Circuit Device Patent Applications. For example, in one embodiment, an integrated circuit device includes memory section (having, for example, PD or FD SOI memory transistors) and logic section (having, for example, high performance transistors, such as FinFET, multiple gate transistors, and/or non-high performance transistors (for example, single gate transistors that do not possess the performance characteristics of high performance transistors—not illustrated)). Again, the entire contents of the Integrated Circuit Device Patent Applications, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference.

As noted above, the memory cell and/or memory cell array, as well as the circuitry of the present inventions may be implemented in an integrated circuit device having a memory portion and a logic portion (see, for example, FIGS. 12A and 12C), or an integrated circuit device that is primarily a memory device (see, for example, FIG. 12B). The memory array may include a plurality of memory cells arranged in a plurality of rows and columns wherein each memory cell includes a transistor (whether fabricated in a bulk-type material or SOI material), for example, an electrically floating body transistor. The memory arrays may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, data sense circuitry (for example, sense amplifiers or comparators), memory cell selection and control circuitry (for example, word line and/or source line drivers), as well as row and column address decoders) may include P-channel and/or N-channel type transistors.

Further, circuitry that is peripheral to the memory array may be comprised of N-channel, P-channel and/or both types of transistors, as well as partially depleted and/or fully depleted type transistors. For example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein) may include fully depleted type transistors (whether P-channel and/or N-channel type). Alternatively, such circuitry may include partially depleted type transistors (whether P-channel and/or N-channel type). There are many techniques to integrate both partially depleted and/or fully depleted type transistors on the same substrate (see, for example, U.S. Non-Provisional patent application Ser. No. 10/487,157 (U.S. Patent Application Publication No. 2004/0238890), which was filed by Fazan et al. on Feb. 18, 2004 and entitled “Semiconductor Device”. All such techniques, whether now known or later developed, are intended to fall within the scope of the present inventions.

As mentioned above, transistors of the memory cells may be a symmetrical or non-symmetrical device. Where transistor is symmetrical, the source and drain regions are essentially interchangeable. However, where transistor is a non-symmetrical device, the source or drain regions of transistor have different electrical, physical, doping concentration and/or doping profile characteristics. As such, the source or drain regions of a non-symmetrical device are typically not interchangeable. This notwithstanding, the drain region of the electrically floating N-channel transistor of the memory cell (whether the source and drain regions are interchangeable or not) is that region of the transistor that is connected to the bit line/sense amplifier.

It should be noted that while each memory cell in the exemplary embodiments (described above) includes one transistor, the memory cell may include two transistors, as described and illustrated in application Ser. No. 10/829,877, which was filed by Ferrant et al. on Apr. 22, 2004 and entitled “Semiconductor Memory Cell, Array, Architecture and Device, and Method of Operating Same” (U.S. Patent Application Publication No. US 2005/0013163). For the sake of brevity, those discussions will not be repeated.

The above embodiments of the inventions are merely exemplary. They are not intended to be exhaustive or to limit the inventions to the precise forms, techniques, materials and/or configurations disclosed. Many modifications and variations are possible in light of this disclosure. For example, as mentioned above, the illustrated/exemplary voltage levels to implement the read and write operations are merely exemplary. The indicated voltage levels may be relative or absolute. Alternatively, the voltages indicated may be relative in that each voltage level, for example, may be increased or decreased by a given voltage amount (for example, each voltage may be increased or decreased by 0.1, 0.15, 0.25, 0.5, 1, 2 (etc) volts) whether one or more of the voltages (for example, the source, drain or gate voltages) become or are positive and negative.

It is to be understood that other embodiments may be utilized and operational changes may be made without departing from the scope of the present inventions. As such, the scope of the inventions is not limited solely to the description above because the description of the above embodiments has been presented for the purposes of illustration and description.

It should be noted that the term “circuit” means, among other things, a single component or a multiplicity of components (whether in integrated circuit form or otherwise), which are active and/or passive, and which are coupled together to provide or perform a desired operation. The term “circuitry” means, among other things, a circuit (whether integrated or otherwise), or a group of circuits (whether integrated or otherwise). The term “to sense a/the data state stored in memory cell” means, among other things, to sample, to sense, to read and/or to determine a/the data state stored in memory cell; “sensing a/the data state stored in memory cell”, “sensed a/the data state stored in memory cell” or the like shall have the same meaning.

Claims

1. A method for biasing an integrated circuit device comprising: applying a plurality of voltage potentials to a memory cell including at least one transistor, wherein applying a plurality of voltage potentials to a memory cell comprises: applying a first voltage potential to a first region via a source line;applying a second voltage potential to a second region via a bit line;applying a third voltage potential to a body region via a word line coupled to a gate disposed over the body region, wherein the body region includes a storage node disposed between the first region and the second region, wherein the storage node of the body region is: (i) located, at least in part, immediately beneath the gate and (ii) separated from portions of the body region by abutting or overlapping first and second junctions of the transistor.

2. The method of claim 1, wherein the memory cell comprises a gate insulator disposed between the gate and the body region.

3. The method of claim 2, further comprising increasing the first voltage applied to the source line from the first voltage potential applied to the source line during a hold operation to perform a write logic low operation.

4. The method of claim 3, further comprising increasing the second voltage potential applied to the bit line from the second voltage potential applied to the bit line during the hold operation to perform the write logic low operation.

5. The method of claim 4, further comprising increasing the third voltage potential applied to the word line from the third voltage potential applied to the word line during the hold operation to perform the write logic low operation.

6. The method of claim 5, wherein the second voltage potential applied to the bit line is equal to the third voltage potential applied to the word line during the write logic low operation.

7. The method of claim 5, wherein the second voltage potential applied to the bit line is higher than the third voltage potential applied to the word line during the write logic low operation.

8. The method of claim 5, wherein the second voltage potential applied to the bit line is increased before an increase of the first voltage potential applied to the source line and an increase of the third voltage potential applied to the word line during the write logic low operation.

9. The method of claim 2, further comprising increasing the first voltage applied to the source line from the first voltage potential applied to the source line during a hold operation to perform a write logic high operation.

10. The method of claim 9, further comprising maintaining the second voltage potential applied to the bit line at the second voltage potential applied to the bit line during the hold operation to perform the write logic high operation.

11. The method of claim 10, further comprising increasing the third voltage potential applied to the word line from the third voltage potential applied to the word line during the hold operation to perform the write logic high operation.

12. The method of claim 10, wherein the third voltage potential applied to the word line is higher than the second voltage potential applied to the bit line during the write logic high operation.

13. The method of claim 10, wherein the third voltage potential applied to the word line is lower than the second voltage potential applied to the bit line during the write logic high operation.

14. The method of claim 2, wherein increasing the first voltage applied to the source line from the first voltage potential applied to the source line during a hold operation to perform a read operation.

15. The method of claim 14, further comprising maintaining the second voltage potential applied to the bit line at the second voltage potential applied to the bit line during the hold operation to perform the read operation.

16. The method of claim 15, further comprising increasing the third voltage potential applied to the word line from the third voltage potential applied to the word line during the hold operation to perform the read operation.

17. The method of claim 16, wherein the second voltage potential applied to the bit line is higher than the third voltage potential applied to the word line during the read operation.

18. The method of claim 17, wherein, in response to the read operation, the transistor generates a punch-through current which is representative of a data state of the memory cell, and wherein data sense circuitry determines the data state of the memory cell at least substantially based on the punch-through current.

19. The method of claim 1, wherein the body region of the transistor is electrically floating.

20. The method of claim 1, wherein the transistor is disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, wherein the body region is disposed between the first region, the second region, a gate insulator, and the insulating region or layer of the substrate.