Claims
- 1. A C-MOS semiconductor memory circuit having a read amplifier and memory cells which are arranged in columns and rows and which can be connected to said read amplifier by selection means, said read amplifier comprising first and second follower amplifiers and a difference amplifier, an output of said read amplifier driving a tristate bus driver, two bit lines, to which a column of memory cells is connected, being connected to a supply line by P-MOS pull-up transistors, said two bit lines being fed to an input and to an inverting input of said difference amplifier, characterized in that each bit line is fed, by said follower amplifier, to the input and the inverting input of the difference amplifier.
- 2. A C-MOS semiconductor memory circuit as claimed in claim 1, characterized in that the follower amplifier comprises two series-arranged N-MOS transistors and that the amplifier is of the source follower type.
- 3. A C-MOS semiconductor memory circuit as claimed in claim 2, characterized in that the difference amplifier and the source follower amplifiers are activated by a common selection signal.
- 4. A C-MOS semiconductor memory circuit as claimed in claim 3, characterized in that a transistor of each follower amplifier is connected between ground and an input of the difference amplifier and that a bit line is connected to the gate electrode of a further transistor, which is connected between an input of the difference amplifier and a supply node for the difference amplifier.
- 5. A C-MOS semiconductor memory circuit having memory cells which are arranged in columns and rows and which can be connected to a read amplifier by selection means, an output of said amplifier driving a tristate bus driver which comprises a C-MOS push-pull output stage having a P-MOS transistor and and N-MOS transistor, and a C-MOS inverting AND gate having two N-MOS transistors, characterized in that the gate electrode of the P-MOS transistor of the output stage is connected to an output of said C-MOS inverting AND gate, an input of which is connected to the output of the read amplifier and a further input of which receives a control signal which brings the two transistors of the push-pull output stage into a turned-off condition, the gate electrode of the N-MOS transistor of the push-pull output stage being connected to a junction of a drain and a source of the two N-MOS transistors of the inverting AND gate.
- 6. A C-MOS semiconductor memory circuit as claimed in claim 5, characterized in that an equalizing transistor is provided in the read amplifier and receives the same control signal as the inverting AND gate.
Priority Claims (1)
Number |
Date |
Country |
Kind |
8602295 |
Sep 1986 |
NLX |
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Parent Case Info
This is a continuation of application Ser. No. 094,225, filed Sept. 8, 1987 now abandoned.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4270190 |
Jindra et al. |
May 1981 |
|
4280065 |
Minato et al. |
Jul 1981 |
|
4504748 |
Oritani |
Mar 1985 |
|
Continuations (1)
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Number |
Date |
Country |
Parent |
94225 |
Sep 1987 |
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