Claims
- 1. A nonvolatile semiconductor memory device with a floating gate structure, comprising:
- a silicon substrate;
- a floating gate electrode composed of 2 to 10 silicon grains for limiting a number of asperities therein, said floating gate electrode having a potential; and
- a control electrode for controlling the potential of said floating gate electrode.
- 2. A nonvolatile semiconductor memory device having a floating gate structure, comprising:
- a silicon substrate having a drain region and a source region;
- a floating gate electrode composed of 2 to 10 polysilicon grains for limiting a number of asperities therein, said floating gate electrode having a potential;
- a first insulation film formed on said floating gate electrode;
- a control gate electrode comprising a polysilicon layer formed on said first insulation film, for controlling the potential of said floating gate electrode;
- a second insulation film formed on the structure, and having contact holes leading to at least one of said drain region and source region; and
- electrode layers extending in said contact holes formed in said second insulation film, and contacting at least one of said drain region and source region.
- 3. A nonvolatile semiconductor memory device with a floating gate structure, comprising:
- a silicon substrate having a drain region and a source region formed therein;
- a first polysilicon layer a having floating gate electrode composed of 2 to 10 polysilicon grains for limiting a number of asperities therein, said floating gate electrode having a potential;
- second polysilicon layers formed on at least one of said drain region and source region;
- a first insulation film formed on said floating gate electrode;
- a third polysilicon layer formed on said first insulation film, forming a control gate electrode for controlling the potential of said floating gate electrode;
- fourth polysilicon layers formed on said second polysilicon layers;
- a second insulation film formed on the structure, and having contact holes formed therein leading to said fourth polysilicon layers; and
- electrode layers extending in said contact holes formed in said second insulation film, and contacting said second polysilicon layers.
- 4. A semiconductor memory device according to claim 3, wherein said fourth polysilicon layers comprise contact holes formed therein and continuous to said contact holes formed in said second insulation film, and wherein said semiconductor memory device further comprises third insulation films formed between said second polysilicon layers and said fourth polysilicon layers, said third insulation films having contact holes formed therein and continuous to said contact holes formed in said fourth polysilicon layers and said second insulation film.
Priority Claims (1)
Number |
Date |
Country |
Kind |
62-593 |
Jan 1987 |
JPX |
|
Parent Case Info
This application is a continuation of application Ser. No. 07/453,109 filed Dec. 22, 1989, now abandoned, which is a continuation of application Ser. No. 07/138,608 filed Dec. 29, 1987, now abandoned.
US Referenced Citations (10)
Foreign Referenced Citations (4)
Number |
Date |
Country |
0164605 |
Dec 1985 |
EPX |
47-11092 |
Jul 1972 |
JPX |
51-18782 |
Jun 1976 |
JPX |
59-125665 |
Jan 1984 |
JPX |
Non-Patent Literature Citations (2)
Entry |
R. M. Anderson et al., "Evidence for Surface asperity mechanism of conductivity in oxide grown on polycrystalline silicon", Journal of Applied Physics, vol. 48 (Sep. 1977) pp. 4834-4836. |
J. Collinge et al., "Field-Effect in Large Grain Polysilicon Transistors," IEEE IEDM Conf. Proc. (1982), pp. 444-447. |
Continuations (2)
|
Number |
Date |
Country |
Parent |
453109 |
Dec 1989 |
|
Parent |
138608 |
Dec 1987 |
|