Claims
- 1. A semiconductor memory device comprising:a main memory divided into a plurality of blocks in the unit of a plurality of columns, including a plurality of memory cells each for storing information, arranged in a plurality of rows and a plurality of columns, a cache memory divided into a plurality of blocks in the unit of the same number of columns as said plurality of columns of said each block of said main memory, including a plurality of storage elements each for storing information, arranged in a plurality of columns, said cache memory storing, on the block basis, information read out from said main memory on the block basis, transfer means connected between said main memory and said cache memory for transferring, on the block basis, information read out from said main memory on the block basis to said cache memory, and transfer control means for controlling said transfer means so that said transfer means selectively transfers information read out from said main memory on the block basis to any of said plurality of blocks of said cache memory.
- 2. The semiconductor memory device of claim 1, wherein said transfer means includes:first transfer gate means provided between said main memory and an internal I/O bank which is inserted between said main memory and said cache memory, for transferring information read out from said main memory on the block basis to said internal I/O band, and second transfer gate means provided between said internal I/O band and said cache memory for transferring said information on the block basis transferred to said internal I/O band, to said cache memory on the block basis.
- 3. The semiconductor memory device of claim 2, wherein said transfer control means applies an output of a block decoder which selects any of said plurality of blocks of said main memory in response to a block selecting address to said first transfer gate means to selectively drive said first transfer gate means, and applies an output of a way decoder which selects any of said plurality of blocks of said cache memory in response to a way selecting address to said second transfer gate means to selectively drive said second transfer gate means.
Priority Claims (2)
Number |
Date |
Country |
Kind |
62-281619 |
Nov 1987 |
JP |
|
62-322126 |
Dec 1987 |
JP |
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CROSS-REFERENCE TO RELATED, U.S. PATENTS
This application is a division of application Ser. No. 08/283,367 filed Aug. 1, 1994 U.S. Pat. No. 5,588,130 which is a Continuation application of application Ser. No. 08/063,487 filed on May 19, 1993 U.S. Pat. No. 5,353,427 which is a Divisional application of application Ser. No. 07/564,657, filed on Aug. 9, 1990, U.S. Pat. No. 5,226,147 which is a continuation of Ser. No. 07/266,601 which which was filed on Nov. 3, 1988.
The following U.S. patents are related to the present application: U.S. Pat. Nos. 4,926,385; 4,953,164; 5,111,386; 5,179,687.
US Referenced Citations (24)
Foreign Referenced Citations (2)
Number |
Date |
Country |
56-77968 |
Jun 1981 |
JP |
61-90396 |
Oct 1988 |
JP |
Non-Patent Literature Citations (3)
Entry |
Asakura et al., “An Experimental 1Mb Cache DRAM with ECC”, 1989 Symposium on VLSI Circuits (May 25-27, 1989), pp. 43-44. |
Asakura et al., “An Experimental 1Mb Cache DRAM with ECC”, IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, pp. 5-10. |
Hidaka et al., “The Cache DRAM Architecture: A DRAM with an On-Chip Cache Memory”, IEEE Micro, (Apr. 1990), pp. 14-24. |
Continuations (2)
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Number |
Date |
Country |
Parent |
08/063487 |
May 1993 |
US |
Child |
08/283367 |
|
US |
Parent |
07/266601 |
Nov 1998 |
US |
Child |
07/564657 |
|
US |