Claims
- 1. A semiconductor memory device comprising:
- a plurality of sectional cell arrays arranged in a row direction and each having a plurality of memory cells arranged in a matrix pattern;
- main word lines each provided in common for a row of all of said sectional cell arrays and responsive to a row select signal;
- section word lines provided for each row of each of said sectional cell arrays and each of said section word lines connected to the corresponding memory cells arranged in each corresponding row of each of said sectional cell arrays, for activating the memory cells connected thereto;
- first and second section select lines provided between a pair of said sectional cell arrays, and responsive to section select signals,
- a plurality of logical circuit groups each provided between a pair of said sectional cell arrays, and each having a plurality of logical circuits each connected to each row of said sectional cell arrays, for activating a section word line when a logical result of a row select signal and a section select signal satisfies a logical condition, each logical circuit including:
- a common inverter provided in common for said pair of said sectional cell arrays; and
- a first circuit for activating a section word line of one of said pair of said sectional cell arrays and a second circuit for activating a section word line of the other of said pair of said sectional cell arrays, said first and second circuits being symmetrical with each other with respect to a column line;
- said first circuit having a first CMOS-type inverter composed of series-connected P-type and N-type transistors, and a first N-type transistor; and
- said second circuit having a second CMOS-type inverter composed of series-connected P-type and N-type transistors, and a second N-type transistor;
- said main word line being connected to said common inverter and to input terminals of the first and second CMOS-type inverters;
- a first section select line being connected to a drain of the first N-type transistor and a source of the P-type transistor of the first inverter, and a second section select line being connected to a drain of the second N-type transistor and a source of the P-type transistor of the second inverter;
- an output of said common inverter being connected to gates of the first and second N-type transistors; and
- a source of the first N-type transistor and an output terminal of the first CMOS-type inverter being connected to a section word line of one of the sectional cell arrays, and a source of the second N-type transistor and an output terminal of the second CMOS-type inverter being connected to a section word line of the other of the sectional cell arrays; and
- bit lines each connected to the memory cells, respectively, for receiving data from the selected memory cells and outputting the received data; and
- a plurality of section select signal output circuits for outputting said section select signals to each said section select line, each section select signal output circuit comprising a power supply circuit with a high driving capacity, wherein said power supply circuit is a BiCMOS logical circuit.
- 2. A semiconductor memory device according to claim 1, wherein said section select signal output circuit further comprising a compensating circuit for compensating a voltage outputted from said BiCMOS logical circuit by a value of a fall of potential.
- 3. A semiconductor memory device according to claim 2, said each section select signal output circuit having said BiCMOS logical circuit as said power supply circuit, an inverter and a P-channel transistor as said compensating circuit, an output terminal of said BiCMOS logical circuit being connected to said section select line, an input terminal of said inverter and the drain of said P-channel transistor, an output terminal of said inverter being connected to the gate of said P-channel transistor, and the source of said P-channel transistor being applied with a power source voltage.
- 4. A semiconductor memory device comprising:
- a plurality of cell array sections, each having a plurality of memory cells disposed in a matrix form, said plurality of cell array sections being juxtaposed in a row direction;
- main word lines, each provided in common for all of said plurality of cell array sections at each row, a row select signal being applied to each said main word line;
- section word lines connected to said memory cells in each said cell array section at each row, for activating said memory cells;
- section select lines provided for each said cell array section, a section selection signal being applied to each said section select line;
- logical circuits provided for each said cell array section, each said logical circuit being connected to each said main word line and said section select line, said logical circuits executing a logical operation between said row select signal and said section select signal, and activating said section select line when said logical operation result satisfies a predetermined logical condition, each said logical circuit including a first inverter, a CMOS type second inverter and an N-channel transistor, each said main word line being connected to the input terminals of said first and second inverters, each said section select line being connected to the drain of said N-channel transistor and the source of a P-channel transistor of said second inverter, the gate of said N-channel transistor being connected to the output terminal of said first inverter, and each said section word line being connected to the source of said N-channel transistor and the output terminal of said second inverter;
- bit lines connected to each memory cell for receiving data from a selected memory cell and outputting said data;
- a plurality of section select signal output circuits for outputting said section select signal to each said section select line, each said section select signal output circuit comprising a power supply circuit with a high driving capacity, said power supply circuit being a BiCMOS logical circuit; and
- a compensating circuit in said section select signal output circuit which compensates for the voltage outputted from said BiCMOS logical circuit by a drop in potential;
- each select signal output circuit having said BiCMOS logical circuit as said power supply circuit and said compensating circuit, said compensating circuit comprising an inverter, a delay circuit and serially connected first and second P-channel transistors, an output terminal of said BiCMOS logical circuit being connected to said section select line, an input terminal of said inverter and an input terminal of said delay circuit, an output terminal of said inverter being connected to the gate of said first P-channel transistor, an output terminal of said delay circuit being connected to the gate of said second P-channel transistor, the source of said first P-channel transistor being supplied with a power source voltage, and the drain of said second P-channel transistor being connected to said section select line.
- 5. A semiconductor memory device according to claim 4, wherein said delay circuit includes a plurality of serially connected inverters.
- 6. A semiconductor memory device comprising:
- a plurality of cell array sections, each having a plurality of memory cells disposed in a matrix form, said plurality of cell array sections being juxtaposed in a row direction;
- main word lines, each provided in common for all of said plurality of cell array sections at each row, a row select signal being applied to each said main word line;
- section word lines connected to said memory cells in each said cell array section at each row, for activating said memory cells;
- section select lines provided for each said cell array section, a section selection signal being applied to each said section select line;
- logical circuits provided for each said cell array section, each said logical circuit disposed between a pair of cell array sections and connected to each said main word line and said section select line, said logical circuits executing a logical operation between said row select signal and said section select signal, and activating said section select line when said logical operation result satisfies a predetermined logical condition, each said logical circuit including a first inverter, a CMOS type second inverter and an N-channel transistor, each said main word line being connected to the input terminals of said first and second inverters, each said section select line being connected to the drain of said N-channel transistor and the source of a P-channel transistor of said second inverter, the gate of said N-channel transistor being connected to the output terminal of said first inverter, and each said section word line being connected to the source of said N-channel transistor and the output terminal of said second inverter;
- bit lines connected to each memory cell for receiving data from a selected memory cell and outputting said data; and
- a plurality of section select signal output circuits for outputting said section select signal to each said section select line, each said section select signal output circuit comprising a power supply circuit with a high driving capacity, each said power supply circuit being a BiCMOS logical circuit:
- each said section select signal output circuit comprising a compensating circuit compensating for the voltage outputted from said BiCMOS logical circuit by a drop in potential;
- said each select signal output circuit having said BiCMOS logical circuit as said power supply circuit and said compensating circuit, said compensating circuit comprising an inverter, a delay circuit and serially connected first and second P-channel transistors, an output terminal of said BiCMOS logical circuit being connected to said section select line, an input terminal of so said inverter and an input terminal of said delay circuit, an output terminal of said inverter being connected to the gate of said first P-channel transistor, an output terminal of said delay circuit being connected to the gate of said second P-channel transistor, the source of said first P-channel transistor being applied with a power source voltage, and the drain of said second P-channel transistor being connected to said section select line.
- 7. A semiconductor memory device according to claim 6, wherein said delay circuit includes a plurality of serially connected inverters.
- 8. A semiconductor memory device comprising:
- a plurality of cell array sections, each having a plurality of memory cells disposed in a matrix form, said plurality of cell array sections being juxtaposed in a row direction;
- main word lines, each provided in common for all of said plurality of cell array sections at each row, a row select signal being applied to each said man word line;
- section word lines connected to said memory cells in each said cell array section at each row, for activating said memory cells;
- section select lines provided for each said cell array section, a section selection signal being applied to each said section select line;
- logical circuits provided for each said cell array section, each said logical circuit being connected to each said main word line and said section select line, said logical circuits executing a logical operation between said row select signal and said section select signal, and activating said section select line when said logical operation result satisfies a predetermined logical condition, each said logical circuit including a first inverter, a CMOS type second inverter and an N-channel transistor, each said main word line being connected to the input terminals of said first and second converters, each said section select line being connected to the drain of said N-channel transistor and the source of a P-channel transistor of said second inverter, the gate of said N-channel transistor being connected to the output terminal of said first inverter, and each said section word line being connected to the source of said N-channel transistor and the output terminal of said second inverter;
- bit lines connected to each memory cell for receiving data from a selected memory cell and outputting said data; and
- a plurality of section select signal output circuits for outputting said select signal to each said section select line, said each section select signal output circuit comprising a power supply circuit with a high driving capacity, said power supply circuit being a BiCMOS logical circuit, and further including a compensating circuit for compensating for voltage outputted from said BiCMOS logical circuit by fall of potential;
- wherein said each section select signal output circuit having said BiCMOS logical circuit as said power supply circuit, and said compensating circuit, said compensating circuit comprising a delay circuit, a second logical circuit and a P-channel transistor, an output terminal of said BiCMOS logical circuit being connected to said section select line, an input terminal of said delay circuit, the drain of said P-channel transistor and a first input terminal of said second logical circuit, an output of said delay circuit being connected to a second input terminal of said second logical circuit, an output terminal of said second logical circuit being connected to the gate of said P-channel transistor, and the source of said P-channel transistor being applied with a power source voltage.
- 9. A semiconductor memory device according to claim 8, wherein said delay circuit includes a plurality of serially connected inverters.
- 10. A semiconductor memory device according to claim 8, wherein said second logical circuit has a NAND operation function, and said delay circuit includes an even number of serially connected inverters.
- 11. A semiconductor memory device comprising:
- a plurality of cell array sections, each having a plurality of memory cells disposed in a matrix form, said plurality of cell array sections being juxtaposed in a row direction;
- main word lines, each provided in common for all of said plurality of cell array sections at each row, a row select signal being applied to each said main word line;
- section word lines connected to said memory cells in each said cell array section at each row, for activating said memory cells;
- section select lines provided for each said cell array section, a section selection signal being applied to each said section select line;
- logical circuits provided for each said cell array section, each said logical circuit being disposed between a pair of cell array sections and connected to each said main word line and said section select line, said logical circuits executing a logical operation between said row select signal and said section select signal, and activating said section select line when said logical operation result satisfies a predetermined logical condition, each said logical circuit including a first inverter, a CMOS type second inverter and an N-channel transistor, each said main word line being connected to the input terminals of said first and second inverters, each said section select line being connected to the drain of said N-channel transistor and the source of a P-channel transistor of said second inverter, the gate of said N-channel transistor being connected to the output terminal of said first inverter, and each said section word line being connected to the source of said N-channel transistor and the output terminal-of said second inverter;
- bit lines connected to each memory cell for receiving data from a selected memory cell and outputting said data; and
- a plurality of section select signal output circuits for outputting said section select signal to each said section select line, said each section select signal output circuit comprising (1) a power supply circuit with a high driving capacity, said power supply circuit being a BiCMOS logical circuit, and (2) a compensating circuit for compensating for a voltage outputted from said BiCMOS logical circuit by the value of a potential drop.
- 12. A semiconductor memory device according to claim 11, wherein said delay circuit includes a plurality of serially connected inverters.
- 13. A semiconductor memory device according to claim 11, wherein said second logical circuit has a NAND operation function, and said delay circuit includes an even number of serially connected-inverters. .Iadd.
- 14. A semiconductor memory device comprising: a plurality of cell array sections, each having a plurality of memory cells disposed in a matrix form, said plurality of cell array sections being juxtaposed in a row direction; main word lines, each provided in common for all of said plurality of cell array sections at each row, a row select signal being applied to each said main word line; section word lines connected to said memory cells in each said cell array section at each row, for activating said memory cells; section select lines provided for each said cell array section, a section selection signal being applied to each said section select line; logical circuits provided for each said cell array section, said logical circuits executing a logical operation between said row select signal and said section select signal, and activating said section select line when said logical operation result satisfies a predetermined logical condition, each said logical circuit including a CMOS type inverter and an N-channel transistor, each said main word line being connected to the input terminal of said inverter, each said section select line being connected to the drain of said N-channel transistor and the source of a P-channel transistor of said inverter, the rate of said N-channel transistor being supplied with an inverted signal which is complementary to the row select signal applied to each said main word line and each said section word line being connected to the source of said N-channel transistor and the output terminal of said inverter; bit lines connected to the memory cells for receiving data from a selected memory cell and outputting said data; and a plurality of section select signal output circuits for outputting said section select signal to each said section select line, said each section select signal output circuit having a power supply circuit comprising a switch to operably connect the section select signal to a power supply without any voltage drop. .Iaddend..Iadd.15. A semiconductor memory device, as recited in claim 14,
- wherein the switch includes a transistor. .Iaddend..Iadd.16. A semiconductor memory device, as recited in claim 14, further comprising a complementary signal line arranged in parallel to the main word line and connected to the logical circuits, the complementary signal line transferring the inverted signal. .Iaddend..Iadd.17. A semiconductor memory device, as recited in claim 15, further comprising a common circuit connected to the complementary signal line for generating the inverted signal. .Iaddend..Iadd.18. A semiconductor memory device, as recited in claim 14, wherein diffusion layers of said inverter and said N-channel transistor are used in common. .Iaddend..Iadd.19. A semiconductor memory device comprising: a plurality of cell array sections, each having a plurality of memory cells disposed in a matrix form, said plurality of cell array sections being juxtaposed in a row direction; main word lines, each provided in common for all of said plurality of cell array sections at each row, a row select signal being applied to each said main word line; section word lines connected to said memory cells in each said cell array section at each row, for activating said memory cells; section select lines provided for each said cell array section, a section selection signal being applied to each said section select line; logical circuits provided for each said cell array section, said logical circuits executing a logical operation between said row select signal and said section select signal, and activating said section select line when said logical operation result satisfies a predetermined logical condition, each said logical circuit including a CMOS type inverter and an N-channel transistor, each said main word line being connected to the input terminal of said inverter, each said section select line being connected to the drain of said N-channel transistor and the source of a P-channel transistor of said inverter, the gate of said N-channel transistor being supplied with an inverted signal which is complementary to the row select signal applied to each said main word line and each said section word line being connected to the source of said N-channel transistor and the output terminal of said inverter; bit lines connected to the memory cells for receiving data from a selected memory cell and outputting said data; and a plurality of section select signal output circuits for outputting said section select signal to each said section select line, said each section select signal output circuit having connecting means for connecting the section select line and a power supply without any voltage drop. .Iaddend..Iadd.20. A semiconductor memory device, as recited in claim 19, wherein the connection means includes a transistor. .Iaddend.
Priority Claims (1)
Number |
Date |
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3-157112 |
Jan 1991 |
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Parent Case Info
This application is a continuation of application Ser. No. 07/905,416, filed Jun. 29, 1992, now abandoned.
US Referenced Citations (5)
Foreign Referenced Citations (3)
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61-20292 |
Jan 1986 |
JPX |
61-20293 |
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1245489 |
Sep 1989 |
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Continuations (1)
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Number |
Date |
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905416 |
Jun 1992 |
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Reissues (1)
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Number |
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328049 |
Oct 1994 |
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