Claims
- 1. A semiconductor memory device comprising:
- a semiconductor substrate of a first conductivity type having an insulating film for isolating elements formed on a prescribed region of a main surface of said semiconductor substrate;
- a pair of impurity regions of a second conductivity type formed spaced apart from each other by a prescribed distance on the main surface of said semiconductor substrate;
- a first conductive layer formed on the main surface of said semiconductor substrate positioned between said pair of impurity regions with a first insulating film positioned between said first conductive layer and said semiconductor substrate;
- a second conductive layer formed on and passing over the surface of said insulating film for isolating elements;
- second and third insulating films covering outer surfaces of said first and second conductive layers, respectively;
- a first electrode layer connected to one of said pair of impurity regions extending from a position above said second insulating film covering said first conductive layer to a position above said third insulating film covering said second conductive layer;
- a dielectric layer including a first portion covering a rear surface of the first electrode layer, a second portion covering upper and side surfaces of the first electrode layer, and a third portion covering a surface of an impurity region to which the first electrode layer is connected; and
- a second electrode layer covering the surfaces of the first, second and third portions of said dieletric layer forming a capacitor structure comprising said second electrode, said third portion and said impurity region, wherein said second electrode layer and said third dielectric layer portion are fully separated from said first electrode layer by said first dielectric layer portion formed in contact with the surface of the impurity region, and wherein said third portion of the dielectric layer is fully separated from said third insulating film and formed in contact with the surface of said impurity region.
- 2. A semiconductor memory device according to claim 1, wherein
- said first and third portions of said dielectric layer are formed of different materials.
- 3. A semiconductor memory device according to claim 1, wherein
- said second electrode layer comprises at least a first portion positioned between said first conductive layer and said first electrode layer and a second portion position between said second conductive layer and said first electrode layer.
- 4. A semiconductor memory device according to claim 2, wherein
- said third portion of said dielectric layer is formed of an oxide film.
- 5. A semiconductor memory device according to claim 1, wherein said third insulating film is fully separated from the surface of said impurity region by said insulating film for isolating elements.
- 6. A semiconductor memory device according to claim 1, wherein said second electrode layer fully separates said third insulating film from said first portion of the dielectric layer.
- 7. A semiconductor memory device according to claim 1, wherein said third insulating film is fully separated from said first electrode layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
63-312420 |
Dec 1988 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 07/446,744 filed Dec. 6, 1989, U.S. Pat. No. 5,177,574.
US Referenced Citations (10)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0295709 |
Dec 1988 |
EPX |
1-154552 |
Jun 1989 |
JPX |
2-94554 |
Apr 1990 |
JPX |
Non-Patent Literature Citations (3)
Entry |
T. Kisu, "A Novel Storage Capacitance Enlargement Structure Using a Double-Stacked Storage Node in STC DRAM Cell," 20th International Conf. on Solid State Devices and Materials, 1988, pp. 581-584. |
T. Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS," IEDM, 1988, pp. 592-595. |
R. M. Geffkan et al., "Process for High-Capacitance Single-Device Memory Cell", IBM Technical Disclosure Bulletin, vol. 21, No. 6, Nov. 1978, pp. 2257-2259. |
Continuations (1)
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Number |
Date |
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Parent |
446744 |
Dec 1989 |
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