Semiconductor memory device having reduced voltage coupling between bit lines

Abstract

An enhanced semiconductor memory device capable of eliminating or minimizing a cell data flip phenomenon caused by capacitive voltage coupling between bit lines in different bit line pairs. Each memory cell is connected to a word line and between a pair of bit line. A first precharging and equalizing circuit us connected to a first bit line pair and a second precharging and equalizing circuit us connected to an adjacent second bit line pair. The first and second precharging and equalizing circuit are activated independently and at different times in order to reduce voltage coupling between neighboring bit lines in different bit line pairs, thereby minimizing or eliminating a cell data flip phenomenon of a neighboring memory cell caused by voltage coupling between bit lines.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a circuit diagram of a representative portion of a cell core circuit of a conventional SRAM;

FIG. 2 is a circuit block diagram illustrating the memory cell array structure in which memory cells of FIG. 1 are connected to capacitively coupled bit line pairs;

FIG. 3 is a timing diagram illustrating the operation timing for various signals in FIG. 1;

FIG. 4 is a timing diagram illustrating simulation waveforms of various signals in FIG. 1;

FIG. 5 is a circuit diagram of a representative portion of a cell core circuit of an SRAM according to an embodiment of the present invention;

FIG. 6 is a circuit diagram illustrating an equalizing driver in FIG. 5;

FIG. 7A is a timing diagram illustrating operation timing for various signals in the SRAM of FIG. 5;

FIG. 7B is a timing diagram illustrating simulation waveforms of various signals in the SRAM of FIG. 5;

FIGS. 8A and 8B are timing diagrams illustrating a comparison in write operation timing between a conventional technique and an embodiment of the present invention, respectively;

FIG. 9 is a timing diagram illustrating simulation waveforms of write operation in the SRAM of FIG. 5;

FIG. 10 is a timing diagram illustrating operation timing for various signals in the equalizing driver shown in FIG. 6;

FIG. 11 is a circuit diagram illustrating an implementation of a write driver in the SRAM of FIG. 5;

FIG. 12 is a circuit diagram illustrating an implementation of a sense amplifier in the SRAM of FIG. 5;

FIG. 13 is a combination of circuit diagram and timing diagram illustrating capacitive voltage coupling between bit lines during a read operations in a conventional bit line layout structure; and

FIG. 14 is a wiring diagram illustrating a bit line layout structure, solving a capacitive coupling problem in FIG. 13, according to a variant of the present invention.

Claims

1. A semiconductor memory device, comprising: a memory cell array having a matrix of memory cells connected, each memory cell being connected to a word line and between a pair of bit lines; anda first precharging and equalizing circuit connected to a first bit line pair connected to a first memory cell connected to the first word line; anda second precharging and equalizing circuit connected to a second bit line pair connected to a second memory cell connected to the first word line, wherein the first memory cell is adjacent to the second memory cell.

2. The device according to claim 1, further comprising, a third precharging and equalizing circuit connected to a third bit line pair connected to a third memory cell connected to the first word line, wherein the third memory cell is adjacent to the second memory cell.

3. The device according to claim 2, further comprising, a bit line coupling reduction unit for first applying an equalization release signal to the first precharging and equalizing circuit when a data access mode of operation is initiated, and then applying equalization release signals to the second and third precharging and equalizing circuits connected after a predetermined time lapses.

4. The device according to claim 3, wherein the bit line coupling reduction unit is an equalizing driver.

5. The device according to claim 4, wherein the equalizing driver operates sixteen precharging and equalizing circuits.

6. The device according to claim 1, wherein a word line connected to the first memory cell is enabled a predetermined time after the first precharging and equalizing circuit is disabled.

7. The device according to claim 1, wherein a word line connected to the first memory cell is enabled when the second precharging and equalizing circuit is disabled.

8. The device according to claim 1, wherein the semiconductor memory device is a static random access memory including a the first and second memory cells, each of the first and second memory cells includes six transistors.

9. The device according to claim 8, wherein the six transistors comprise three-dimensional stack memory cells formed on different layers.

10. The device according to claim 1, wherein the first bit line pair is a twisted pair of conductors twisted per each predetermined number of word lines.

11. The device according to claim 10, wherein the first and second bit line pairs are twisted every 1024 word lines.

12. A semiconductor memory device, comprising: an array of memory cells, each memory cell being connected to a word line pair and between a pair of bit lines; anda first precharging and equalizing circuit connected to a first bit line pair connected to a first memory cell connected to a first word line; anda second precharging and equalizing circuit connected to a second bit line pair connected to a second memory cell connected to the first word line, wherein the first memory cell is adjacent to the second memory cell.

13. The device according to claim 12, further comprising, a third precharging and equalizing circuit connected to a third bit line pair connected to a third memory cell connected to the first word line, wherein the third memory cell is adjacent to the second memory cell.

14. The device according to claim 13, further comprising an equalizing driver for applying an equalization release signal to the first precharging and equalizing circuit, and then applying equalization release signals to the second and third precharging and equalizing circuits when the first word line is activated after a write driver is enabled.

15. The device according to claim 14, wherein the equalizing driver operates sixteen precharging and equalizing circuits.

16. The device according to claim 12, wherein the bit line pairs are twisted per each predetermined number of word lines.

17. The device according to claim 16, wherein the bit line pairs are twisted per 1024 word lines.

18. The device according to claim 12, wherein the semiconductor memory device includes a write driver and a sense amplifier.

19. The device according to claim 12, wherein the semiconductor memory device is a static random access memory including a the first and second memory cells, each memory cell includes six transistors.

20. The device according to claim 19, wherein the six transistors comprise three-dimensional single stack memory cells formed on different layers.

21. A static random access semiconductor memory device, comprising: an array of memory cells, each memory cell being connected to a word line and between a pair of bit lines; anda word line enable delay unit for delaying a driving time point of a selected word line in a data access mode of operation from a time point at which a bit line pair of a selected memory cell is equalized.

22. The device according to claim 21, wherein the data access mode of operation is a write mode of operation.

23. The device according to claim 21, wherein the bit line pairs are twisted per each predetermined number of word lines.

24. A method for performing a write operation in a semiconductor memory device comprising a first memory cell connected to a first word line and between a first pair of bit lines and a second memory cell connected to the first word line and between a second pair of bit lines, the method comprising: applying an equalization release signal to a first precharging and equalizing circuit connected to the first bit line pair;applying an equalization release signal to a second precharging and equalizing circuit connected to the second bit line pair when the first word line is activated after a write driver is enabled; andwriting write data to the first memory cell before the second precharging and equalizing circuit connected to the second bit line pair is disabled.

25. A method for performing write operation in a semiconductor memory device comprising an array of memory cells, each memory cell having three-dimensional stack and being connected to a word line and between a pair of bit lines, the method comprising: applying an equalization release signal to a first precharging and equalizing circuit connected to a first pair of bit lines;applying equalization release signals to a second precharging and equalizing circuit connected to a second pair of bit lines and to a third precharging and equalizing circuit connected to a third pair of bit lines when a word line is activated after a write driver is enabled; andwriting write data to a first memory cell connected to the word line and between the first pair of bit lines immediately after the second and third precharging and equalizing circuits are disabled.