Claims
- 1. A semiconductor memory device comprising:
- a memory cell array having a plurality of bit lines disposed in a parallel manner, a plurality of word lines disposed in a parallel manner and intersected with said bit lines perpendicularly, a plurality of memory cells coupled between said bit and word lines for storing data therein;
- a plurality of sense amplifiers disposed at both sides of said memory cell array in such manner that odd numbered sense amplifiers are disposed at one side of said memory cell array and even numbered sense amplifiers are disposed at the other side of said memory cell, said odd numbered sense amplifiers being coupled to odd numbered bit lines and said even numbered sense amplifiers being coupled to said even numbered bit lines;
- a plurality of sub bit lines for coupling said sense amplifiers disposed at both sides of said memory cell array;
- voltage control circuits coupled to said sense amplifiers for restricting an amplitude of signal voltages appearing on said sub bit lines; and
- a pair of data busses coupled to said sub bit lines.
- 2. A semiconductor memory device of claim 1, further comprising a plurality of middle amplifiers coupled between said sub bit lines and said data busses.
- 3. A semiconductor memory device of claim 2, wherein each of said middle amplifiers is of a flip-flop type.
- 4. A semiconductor memory device of claim 2, wherein each of said middle amplifiers is of a current-mirror-type.
- 5. A semiconductor memory device of claim 1, further comprising a single middle amplifier coupled to said data busses.
- 6. A semiconductor memory device of claim 5, further comprising a switching circuit disposed between said middle amplifier and said sub bit lines.
- 7. A semiconductor memory device comprising;
- a memory cell array having a plurality of blocks, each block including a memory cell sub array, and sense amplifiers disposed at both sides of said memory cell sub array;
- a plurality of sub bit lines disposing over said plurality of blocks and coupled to said sense amplifiers in each block;
- voltage control circuits coupled to said sense amplifiers for restricting an amplitude of signal voltages appearing on said sub bit lines;
- a pair of data busses coupled to said sub bit lines;
- a column decoder unit disposed at one side of said memory cell array; and
- a row decoder unit disposed at another side of said memory cell array.
Priority Claims (3)
Number |
Date |
Country |
Kind |
61-95364 |
Apr 1986 |
JPX |
|
62-93604 |
Apr 1987 |
JPX |
|
62-164544 |
Jul 1987 |
JPX |
|
Parent Case Info
This is a Continuation-In-Part of parent application Ser. No. 040,471, filed Apr. 20, 1987, now U.S. Pat. No. 4,807,194.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
4700328 |
Burghard |
Oct 1987 |
|
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
40471 |
Apr 1987 |
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