SEMICONDUCTOR MEMORY DEVICE, POWER SUPPLY DETECTOR AND SEMICONDUCTOR DEVICE

Abstract

A semiconductor memory device comprises a n-channel type MOSFET in which a drain and a gate are connected to an external power supply and a source and a back gate are connected each other, a node connected to the source and the back gate of the n-channel type MOSFET, and a detector for detecting an input of the external power supply based on a potential of the node

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a drawing showing a structure of a power supply input detection circuit of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram for explaining a power-on sequence of the semiconductor memory device using the power supply input detection circuit shown in FIG. 1.

FIG. 3 is a drawing showing a temperature dependency of a node A of the power supply input detection circuit shown in FIG. 1.

FIG. 4 is a drawing showing a temperature dependency of an output of the power supply input detection circuit shown in FIG. 1.

FIG. 5 is a drawing showing a comparison of the temperature dependency of output between the power supply input detection circuit shown in FIG. 1 and a power supply input detection circuit shown in FIG. 9.

FIG. 6 is a drawing showing a setting range of output of the power supply input detection circuit shown in FIG. 1

FIG. 7 is a block diagram for explaining the power-on sequence using a power supply input detection circuit according to a second embodiment.

FIG. 8 is a drawing showing a structure of the power supply input detection circuit shown in FIG. 7.

FIG. 9 is a drawing showing a structure of conventional and typical power supply input detection circuit in comparison with the present invention.

FIG. 10 is a drawing showing a temperature dependency of a node A in the typical power supply input detection circuit shown in FIG. 9.

FIG. 11 is a drawing showing a temperature dependency of output of the typical power supply input detection circuit shown in FIG. 9.

FIG. 12 is a drawing showing a structure of option fuse latch circuit shown in FIG. 2.

FIG. 13 is a drawing showing a setting range of output in the typical power supply input detection circuit shown in FIG. 9.

Claims

1. A semiconductor memory device, comprising: an n-channel type MOSFET in which a drain and a gate thereof are connected to an external power supply, and a source and a back gate thereof are connected each other;a node which is connected to the source and the back gate of the n-channel type MOSFET; anda detector for detecting an applying of the external power supply based on a potential of the node.

2. The semiconductor memory device according to claim 1, wherein the detector comprises an n-channel type MOSFET and a p-channel type MOSFET which are connected complementarily each other

3. The semiconductor memory device according to claim 1, further comprising an external voltage detector which outputs a power supply detection signal by detecting that a voltage of the external power supply reaches to a predetermined value by receiving an output of the detector.

4. The semiconductor memory device according to claim 3, further comprising: an internal power generator which outputs an internal power supply based on the power supply detection signal; anda fuse-latch circuit which latches fuse data using the internal power supply.

5. The semiconductor memory device according to claim 4, wherein the predetermined value of the external voltage detector is a voltage value of which the fuse-latch circuit can latch the fuse data in the fuse-latch circuit.

6. The semiconductor memory device according to claim 3, wherein the external voltage detector comprises a quasi-fuse-latch circuit having a circuit constant which is substantially an equal circuit constant to that of the fuse-latch circuit.

7. The semiconductor memory device according to claim 1, further comprising an inverter which reverses an output of the detector.

8. A power supply detector, comprising: a first n-channel type MOSFET in which a drain and a gate thereof are connected to a power supply, and a source and a back gate thereof are connected each other; anda second n-channel type MOSFET and a first p-channel type MOSFET which are connected complementarily each other, each of the second n-channel type MOSFET and the first p-channel type MOSFET having a gate connected to the source and the back gate of the first n-channel type MOSFET and a drain outputting a detection output which detects an applying of the power supply.

9. The power supply detector according to claim 8, further comprising an inverter which reverses the detection output.

10. The power supply detector according to claim 9, wherein the inverter comprises a plurality of inverters of which uneven numbers of inverters are series connected.

11. A semiconductor device which has a power detector, comprising: a first n-channel type MOSFET in which a drain and a gate thereof are connected to an external power supply, and a source and a back gate thereof are connected each other; anda second n-channel type MOSFET and a first p-channel type MOSFET which are connected complementarily each other, each of the second n-channel type MOSFET and the first p-channel type MOSFET having a gate connected to the source and the back gate of the first n-channel type MOSFET and a drain outputting a detection output which detects an applying of the external power supply.

12. The semiconductor device according to claim 11, further comprising an external voltage detector for outputting a power supply detection signal by detecting that a voltage of the external power supply reaches to a predetermined value by receiving an output of the power supply detector.

13. The semiconductor device according to claim 12, further comprising: an internal power generator for outputting an internal power supply to be used within the semiconductor device; anda fuse-latch circuit for latching fuse data by use of the internal power supply.

14. The semiconductor device according to claim 12, wherein the predetermined value of the external voltage detector is a voltage of which the fuse-latch circuit can latch the fuse-latch data.

15. The semiconductor device according to claim 12, wherein the external voltage detector comprises a quasi-fuse-latch circuit having a circuit constant which is substantially an equal circuit constant to that of the fuse-latch circuit.

16. The semiconductor device according to claim 11, further comprising an inverter which reverses an output of the power detector.

17. The semiconductor device according to claim 16, wherein the inverter comprises a plurality of inverters of which uneven numbers of inverters are series connected.

18. The semiconductor device according to claim 16, wherein the inverter comprises: a first inverter, in which an input thereof and respective drains of the second n-channel type MOSFET and the first p-channel type MOSFT connected complementarily are connected;a second inverter in which an input thereof and an output of the first inverter are connected; anda third converter in which an input thereof and an output of the second inverter are connected.

19. The semiconductor device according to claim 18, further comprising: a third n-channel type MOSFET and a second p-channel type MOSFET which are complementarily connected,wherein the output of the first inverter is connected to a gate of the second p-channel type MOSFET, an output of the third inverter is connected to a gate of the third n-channel type MOSFET, and respective drains of the third n-channel type MOSFET and the second p-channel type MOSFET output a quasi-fuse data.