Claims
- 1. A semiconductor memory device comprising:
- a memory cell array region including memory cells arranged in an array form;
- a plurality of word lines arranged within said memory cell array region in parallel to one another;
- first and second row decoders arranged respectively on both sides of said memory cell array region;
- an insulating film covering said word lines; and
- a plurality of metallic wirings formed on said insulating film and electrically connected to said word lines by means of contact parts, said metallic wirings having step portions in an area where said metallic wirings pass from one layer to another layer, each of alternate ones of said metallic wirings having an elongated end portion to be connected to said first row decoder and each of remaining ones of said metallic wirings having an elongated end portion to be connected to said second row decoder, said elongated end portions of said metallic wirings having a width greater than remaining portions of said metallic wirings, said greater width being provided substantially at said step portions.
- 2. The semiconductor memory device as claimed in claim 1, wherein each of said memory cells comprises one insulated gate field effect transistor and one storage capacitor, a part of said word line serving as a gate electrode of said insulated gate field effect transistor, and said storage capacitor being stacked on said insulated gate field effect transistor.
- 3. The semiconductor memory device as claimed in claim 1, wherein the width of the end portion of each of said metallic wirings is about twice as large as the width of said word line.
- 4. The semiconductor memory device as claimed in claim 1, wherein said word line comprises polysilicon and said metallic wiring comprises an aluminum alloy.
Priority Claims (1)
Number |
Date |
Country |
Kind |
3-119681 |
May 1991 |
JPX |
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Parent Case Info
This is a continuation of application No. 07/886,941 filed May 22, 1992, now abandoned.
US Referenced Citations (6)
Foreign Referenced Citations (6)
Number |
Date |
Country |
3447722 |
Jul 1985 |
DEX |
3919625 |
Dec 1989 |
DEX |
58-66343 |
Apr 1983 |
JPX |
62-11262 |
Jan 1987 |
JPX |
62-249478 |
Oct 1987 |
JPX |
63-301544 |
Dec 1988 |
JPX |
Non-Patent Literature Citations (1)
Entry |
IBM Teth Discl Bull, `Generalized Logic Image Masterslice Chip`, vol. 32 No. 8B Jan. 1990, pp. 37-38. |
Continuations (1)
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Number |
Date |
Country |
Parent |
886941 |
May 1992 |
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