Semiconductor memory device

Abstract

In a semiconductor memory device, comprising: a memory cell including a flip-flop; anda memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell,the memory cell power supply circuit suppliesa cell power supply voltage in a first period and a different cell power supply voltage in a second period,a predetermined first power supply voltage in a case where the cell power supply voltage is supplied in a data read cycle and in a case where data is not written to a memory cell to which the cell power supply voltage is supplied in a write cycle, anda second power supply voltage higher than the first power supply voltage in a case where data is written to a memory cell to which the cell power supply voltage is supplied in a write cycle.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device of Reference Example 1.

FIG. 2 is a circuit diagram showing a configuration of a memory cell power supply control circuit of Reference Example 2.

FIG. 3 is a circuit diagram showing a configuration of a memory cell power supply control circuit of Reference Example 3.

FIG. 4 is a circuit diagram showing a configuration of a memory cell of Reference Example 4.

FIG. 5 is a circuit diagram showing a configuration of a memory cell power supply control circuit of Reference Example 5.

FIG. 6 is a circuit diagram showing another configuration of a memory cell power supply control circuit of Reference Example 5.

FIG. 7 is a circuit diagram showing a configuration of a semiconductor memory device having a redundant circuit block of Reference Example 6.

FIG. 8 is a circuit diagram showing a configuration of a semiconductor memory device of Embodiment 1.

FIG. 9 is a circuit diagram showing a configuration of a memory cell of an alternative Embodiment of the semiconductor memory device of Embodiment 1.

FIG. 10 is a circuit diagram showing a configuration of a memory cell power supply control circuit of Embodiment 2.

FIG. 11 is a circuit diagram showing a configuration of a memory cell of Embodiment 3.

FIG. 12 is a circuit diagram showing a configuration of a memory cell power supply control circuit of Embodiment 4.

FIG. 13 is a circuit diagram showing a configuration of a conventional semiconductor memory device.

Claims

1. A semiconductor memory device, comprising: a memory cell including a flip-flop; anda memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell,wherein the memory cell power supply circuit suppliesa cell power supply voltage in a first period and a different cell power supply voltage in a second period,a predetermined first power supply voltage in a case where the cell power supply voltage is supplied in a data read cycle and in a case where data is not written to a memory cell to which the cell power supply voltage is supplied in a write cycle, anda second power supply voltage higher than the first power supply voltage in a case where data is written to a memory cell to which the cell power supply voltage is supplied in a write cycle.

2. The semiconductor memory device of claim 1, wherein: the first power supply voltage is output in response to a write disable control signal or a column non-select signal; andthe second power supply voltage is output in response to a write enable control signal and a column select signal.

3. The semiconductor memory device of claim 1, wherein the memory cell power supply circuit outputs the second power supply voltage by dividing a predetermined voltage.

4. The semiconductor memory device of claim 3, wherein: the memory cell power supply circuit includes a first transistor and a second transistor;the first transistor has a predetermined driving capability, and outputs the first power supply voltage; anda voltage divided by the first transistor and the second transistor is output as the second power supply voltage.

5. The semiconductor memory device of claim 3, wherein a voltage divider ratio of the voltage division is determined according to a threshold voltage of a drive transistor of the flip-flop.

6. The semiconductor memory device of claim 3, wherein a voltage divider ratio of the voltage division is determined according to a threshold voltage of at least one of an access transistor and a load transistor of the flip-flop of the memory cell.

7. The semiconductor memory device of claim 1, wherein the memory cell power supply circuit is formed by a source follower circuit, and at least transistors forming the source follower have the same polarity as that of a drive transistor of the memory cell.

8. The semiconductor memory device of claim 1, wherein the second power supply voltage is supplied to a source terminal of a drive transistor of the memory cell, and a voltage lower than the second power supply voltage is supplied to a substrate of the drive transistor.

9. The semiconductor memory device of claim 1, further comprising a step-down circuit, wherein a step-down voltage is supplied as the first power supply voltage.

10. The semiconductor memory device of claim 3, wherein a voltage divider ratio of the voltage division is determined according to a temperature of the semiconductor memory device.

11. The semiconductor memory device of claim 3, wherein: a plurality of groups of memory cells are provided, with their memory cell sizes differing from one group to another; anda voltage divider ratio of the voltage division used by the memory cell power supply circuit supplying the second power supply voltage to each memory cell group is determined by the memory cell size.

12. The semiconductor memory device of claim 3, wherein: a plurality of groups of memory cells are provided, with their operating power supply voltages differing from one group to another; anda voltage divider ratio of the voltage division used by the memory cell power supply circuit supplying the second power supply voltage to each memory cell group is determined according to the operating power supply voltage.

13. The semiconductor memory device of claim 3, wherein: a plurality of groups of memory cells are provided, with their transistor threshold voltages differing from one group to another; anda voltage divider ratio of the voltage division used by the memory cell power supply circuit supplying the second power supply voltage to each memory cell group is determined according to the transistor threshold voltage.

14. The semiconductor memory device of claim 1, wherein a driving capability at the time when the memory cell power supply circuit supplies the second power supply voltage is determined according to a temperature of use of the semiconductor memory device.

15. The semiconductor memory device of claim 1, a plurality of groups of memory cells are provided, with their numbers of memory cells connected to a bit line differing from one group to another; anda driving capability at the time when the memory cell power supply circuit supplies the second power supply voltage to each memory cell group is determined according to at least one of the number of memory cells connected to a bit line and a bit line length.

16. The semiconductor memory device of claim 1, wherein: a plurality of groups of memory cells are provided, with their write speed requirements differing from one group to another; anda driving capability at the time when the memory cell power supply circuit supplies the second power supply voltage to each memory cell group is determined according to the write speed requirement.

17. The semiconductor memory device of claim 1, wherein: a plurality of groups of memory cells are provided, with their memory cell sizes differing from one group to another; anda driving capability at the time when the memory cell power supply circuit supplies the second power supply voltage to each memory cell group is determined according to the memory cell size.

18. The semiconductor memory device of claim 1, a plurality of groups of memory cells are provided, with their operating power supply voltages differing from one group to another; anda driving capability at the time when the memory cell power supply circuit supplies the second power supply voltage to each memory cell group is determined based on the operating power supply voltage.

19. The semiconductor memory device of claim 1, wherein: a plurality of groups of memory cells are provided, with their transistor threshold voltages differing from one group to another; anda driving capability at the time when the memory cell power supply circuit supplies the second power supply voltage to each memory cell group is determined according to the transistor threshold voltage.

20. The semiconductor memory device of claim 1, wherein a driving capability when the memory cell power supply circuit supplies the first power supply voltage is determined according to a temperature of use of the semiconductor memory device.

21. The semiconductor memory device of claim 1, wherein: a plurality of groups of memory cells are provided, with their numbers of memory cells connected to a bit line differing from one group to another; anda driving capability at the time when the memory cell power supply circuit supplies the first power supply voltage to each memory cell group is determined according to at least one of the number of memory cells connected to a bit line and a bit line length.

22. The semiconductor memory device of claim 1, wherein: a plurality of groups of memory cells are provided, with their transistor threshold voltages differing from one group to another; anda driving capability at the time when the memory cell power supply circuit supplies the first power supply voltage to each memory cell group is determined according to the transistor threshold voltage.

23. The semiconductor memory device of claim 1, wherein the memory cell power supply circuit can supply the same cell power supply voltage in the first period and in the second period according to a predetermined control signal.

24. The semiconductor memory device of claim 1, wherein the memory cell power supply circuit is configured so that a driving capability at the time when the memory cell power supply circuit supplies the first power supply voltage can be switched from one to another according to a predetermined control signal.

25. The semiconductor memory device of claim 1, wherein: the semiconductor memory device has a function of relieving a defect with redundancy; andin a case where a defect is to be relieved, a supply of a power supply voltage from the memory cell power supply circuit to the memory cell for which a defect is to be relieved is stopped.

26. The semiconductor memory device of claim 1, wherein: the semiconductor memory device has a function of relieving a defect with redundancy; andin a case where a defect is not relieved, a supply of a power supply voltage from the memory cell power supply circuit to a redundant memory cell, which is not to be used, is stopped.

27. A semiconductor integrated circuit, comprising a plurality of semiconductor memory devices of claim 1.

28. A semiconductor memory device, comprising: a memory cell including a flip-flop; anda memory cell power supply circuit for supplying a high voltage cell power supply voltage to the memory cell,wherein the memory cell power supply circuit suppliesa cell power supply voltage in a first period and a different cell power supply voltage in a second period,a predetermined first power supply voltage in a case where the cell power supply voltage is supplied in a data read cycle and in a case where data is not written to a memory cell to which the cell power supply voltage is supplied in a write cycle, anda second power supply voltage lower than the first power supply voltage in a case where data is written to a memory cell to which the cell power supply voltage is supplied in a write cycle,further comprising:a leak compensation circuit for compensating a leak voltage of the memory cell; anda peripheral power supply circuit for supplying a power supply voltage to a peripheral circuit of the memory cell,wherein the memory cell power supply circuit further supplies the first power supply voltage, when the power supply voltage to the peripheral circuit is turned off, andthe leak compensation circuit always operates, when the power supply voltage to the peripheral circuit is turned off.

29. The semiconductor memory device of claim 1, further comprising: a leak compensation circuit for compensating a leak voltage of the memory cell; anda peripheral power supply circuit for supplying a power supply voltage to a peripheral circuit of the memory cell,wherein the memory cell power supply circuit further supplies the first power supply voltage, when the power supply voltage to the peripheral circuit is turned off, andthe leak compensation circuit always operates, when the power supply voltage to the peripheral circuit is turned off.

30. The semiconductor memory device of claim 28, wherein an access transistor of the memory cell is controlled to be turned off, when the power supply voltage to the peripheral circuit is turned off.

31. The semiconductor memory device of claim 30, further comprising: a word line-ground transistor connected between a ground and a word line controlling the access transistor,wherein the word line-ground transistor is turned on so as to control the access transistor to be turned off, when the power supply voltage to the peripheral circuit is turned off.

32. The semiconductor memory device of claim 29, wherein an access transistor of the memory cell is controlled to be turned off, when the power supply voltage to the peripheral circuit is turned off.

33. The semiconductor memory device of claim 30, further comprising: a word line-ground transistor connected between a ground and a word line controlling the access transistor,wherein the word line-ground transistor is turned on so as to control the access transistor to be turned off, when the power supply voltage to the peripheral circuit is turned off.

34. The semiconductor memory device of claim 28, wherein when the power supply voltage to the peripheral circuit is turned off, at least one of the memory cell power supply circuit and the leak compensation circuit supplies a power supply voltage enabling the memory cell to hold memory data.

35. The semiconductor memory device of claim 34, wherein the power supply voltage enabling the memory cell to hold the memory data is generated by serially connecting a transistor having a diode-connected gate, and a transistor controlled by a control signal controlling the power supply voltage to be supplied to the peripheral circuit.

36. The semiconductor memory device of claim 35, wherein the transistor having a diode-connected gate has the same dopant density as a transistor of the memory cell.

37. The semiconductor memory device of claim 29, wherein when the power supply voltage to the peripheral circuit is turned off, at least one of the memory cell power supply circuit and the leak compensation circuit supplies a power supply voltage enabling the memory cell to hold memory data.

38. The semiconductor memory device of claim 37, wherein the power supply voltage enabling the memory cell to hold the memory data is generated by serially connecting a transistor having a diode-connected gate, and a transistor controlled by a control signal controlling the power supply voltage to be supplied to the peripheral circuit.

39. The semiconductor memory device of claim 38, wherein the transistor having a diode-connected gate has the same dopant density as a transistor of the memory cell.