This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-044232, filed Mar. 6, 2014, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to semiconductor memory devices.
Static random access memory (SRAM) is used commonly in a cache memory and so forth because SRAM allows faster access than dynamic random access memory (DRAM).
A normal SRAM cell is formed of a retention section that is formed of four transistors in a cross-coupled arrangement and two transfer transistors that transfer data in and out of the retention section. While data is retained by the retention section, the transfer transistors are set in a floating state such that a leakage current does not flow through the transfer transistors. However, in actuality, there is a possibility that a leakage current flows through the transistors forming the retention section.
Therefore, all the transistors in the SRAM cell may be formed as high-voltage transistors to suppress leakage currents. The high-voltage transistor is formed by increasing a gate length, making a gate oxide film thicker, or increasing the junction depth of a diffusion layer, and has a larger circuit area than a normal transistor. Thus, if all the six transistors in the SRAM cell are formed as high-voltage transistors, the circuit area of the SRAM cell becomes considerably large, which prevents implementation of a high degree of integration.
An embodiment provides a semiconductor memory device having reduced circuit area without degrading leakage characteristics.
In general, according to one embodiment, there is provided a semiconductor memory device including a retention section that retains data by using a first conductivity-type load transistor and a second conductivity-type drive transistor, and a transfer transistor that operates to transfer data to and from the retention section and has a gate length shorter than the gate length of at least one of the drive transistor and the load transistor.
Hereinafter, with reference to the drawings, an example embodiment will be described. In the following examples, the characteristic configuration and operation of a semiconductor memory device will be mainly described, but other configurations and operations may exist in the semiconductor memory devices and these other configurations and operations are also be included in the scope of the disclosure.
The SRAM cell 1 of
The conductivity type of the load transistors Q3 and Q4 is different from the conductivity type of the transfer transistors Q1 and Q2 and the drive transistors Q5 and Q6. For example, the load transistors Q3 and Q4 are PMOS transistors and the transfer transistors Q1 and Q2 and the drive transistors Q5 and Q6 are NMOS transistors.
The load transistor Q3 and the drive transistor Q5 are connected in cascade between a power-supply voltage node (a first reference voltage node) Vcc and a ground node (a second reference voltage node) Vss, thus forming a first inverter. Likewise, the load transistor Q4 and the drive transistor Q6 are also connected in cascade between Vcc and Vss, thus forming a second inverter.
The transfer transistor Q1 performs the transfer of data to and from a connection node of the load transistor Q3 and the drive transistor Q5. Likewise, the transfer transistor Q2 performs the transfer of data to and from a connection node of the load transistor Q4 and the drive transistor Q6.
The transfer transistors Q1 and Q2, according to this embodiment, have a gate length shorter than the gate length of at least one of the load transistors Q3 and Q4 and the drive transistors Q5 and Q6. Hereinafter, an example in which the load transistors Q3 and Q4 and the drive transistors Q5 and Q6 are formed as high-voltage transistors (HV-MOSFETs) and the transfer transistors Q1 and Q2 are formed as low-voltage transistors (LV-MOSFETs) is described. The feature of the HV-MOSFET in this embodiment is that at least the gate length of the HV-MOSFET is longer than the gate length of the LV-MOSFET.
Next, the layout of the SRAM cell 1 according to this embodiment is described with reference to
As is clear from the layout diagram of
On the other hand,
The circuit area of the load transistors Q3 and Q4 and the circuit area of the drive transistors Q5 and Q6 in
As described above, by making the gate length L of the transfer transistors Q1 and Q2 shorter than the gate length L of the drive transistors Q5 and Q6 and the load transistors Q3 and Q4, it is possible to reduce the circuit area of the SRAM cell 1 reliably. Moreover, since a leakage current does not flow through the transfer transistors Q1 and Q2 in principle while data is retained even when the transfer transistors Q1 and Q2 are formed as the LV-MOSFETs, the leakage characteristics are little affected.
In
Moreover, in the above description, an example in which only the gate length L of the transfer transistors Q1 and Q2 is made shorter than the gate length L of the load transistors Q3 and Q4 and the drive transistors Q5 and Q6 is described. However, not only the gate length L of the transfer transistors Q1 and Q2 according to this embodiment, but also the gate oxide film thereof, for example, may be made thinner than the gate oxide film of at least one of the drive transistors Q5 and Q6 and the load transistors Q3 and Q4.
The thinner the gate oxide film 11 is made, the more likely leakage occurs. However, as described above, since the gates of the transfer transistors Q1 and Q2 are in a floating state while data is retained by the retention section 2, the leakage does not become a problem. Therefore, even when the gate oxide film 11 of each of the transfer transistors Q1 and Q2 is made thinner, there is no possibility of impairment of the leakage characteristics.
Furthermore, not only the gate length L of the transfer transistors Q1 and Q2 according to this embodiment, but also the junction depth of a diffusion layer of each of the transfer transistors Q1 and Q2, for example, may be made less than the junction depth of at least one of the drive transistors Q5 and Q6 and the load transistors Q3 and Q4.
As the junction depth 12 of the diffusion layer is reduced, leakage is more likely to occur. However, as described above, since the gates of the transfer transistors Q1 and Q2 are in a floating state while data is retained by the retention section 2, the leakage does not become a problem. Therefore, even when the junction depth 12 of the diffusion layer of each of the transfer transistors Q1 and Q2 is reduced, there is no possibility of impairment of the leakage characteristics.
It is possible to combine the first modified example and the second modified example described above.
When the transfer transistors Q1 and Q2 are formed as the LV-MOSFETs and the drive transistors Q5 and Q6 and the load transistors Q3 and Q4 are formed as the HV-MOSFETs, not only does the gate length L of the LV-MOSFET become shorter but the gate oxide film 11 and the junction depth 12 of the diffusion layer thereof also become thinner and less than the gate oxide film 11 and the junction depth 12 of the diffusion layer of the HV-MOSFET, and the same structure as the structure of
As described above, in this embodiment, since the gate length L of the transfer transistors Q1 and Q2 in the SRAM cell 1 is made shorter than the gate length L of the drive transistors Q5 and Q6 and the load transistors Q3 and Q4, it is possible to reduce the circuit area of the SRAM cell 1 accordingly. Moreover, even when the gate length L of the transfer transistors Q1 and Q2 is made shorter, since the leakage characteristics are not affected much, it is possible to achieve a reduction in the circuit area of the SRAM cell 1 without impairment of the leakage characteristics.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions . Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
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2014-044232 | Mar 2014 | JP | national |