Semiconductor memory device

Abstract

A programmable non-volatile semiconductor memory device includes a select gate 3, arranged in a first region on a substrate, a floating gate 6 arranged in a second region neighboring to the first region, a first diffusion region 7 provided in a third region neighboring to the second region, a control gate 11 arranged on the floating gate 6, and a driving circuit 22 adapted for controlling voltages applied to the substrate 1 (well 1a), select gate 3, first diffusion region 7 and control gate 11. The driving circuit performs control so that, during erasure operation, voltages applied to select gate 3 and the control gate 11 are negative, with the remaining voltage, applied to the substrate 1 (or well 1a), being positive. The device permits erasure operation at a lower voltage.

Description

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a partial plan view schematically showing the constitution of a semiconductor memory device according to a first example of the present invention.

FIG. 2 is a partial cross-sectional view taken along line X-X′ of FIG. 1 showing the constitution of a semiconductor memory device according to the first example of the present invention.

FIG. 3 is a partial plan view showing the constitution of a select gate in an erasure block of the semiconductor memory device according to the first example of the present invention.

FIG. 4 is a schematic view for illustrating a first erasure operation of the semiconductor memory device according to the first example of the present invention.

FIG. 5 is a schematic view for illustrating a second erasure operation of the semiconductor memory device according to the first example of the present invention.

FIG. 6 is a schematic view for illustrating a third erasure operation of the semiconductor memory device according to the first example of the present invention.

FIG. 7 is a schematic view for illustrating an electrical state of a floating gate of the semiconductor memory device according to the first example of the present invention.

FIG. 8 is a schematic view for illustrating a first erasure operation of the semiconductor memory device according to a related art 1, analyzed by the present invention.

FIG. 9 is a schematic view for illustrating a second erasure operation of the semiconductor memory device according to the related art 1, analyzed by the present invention.

Claims

1. A semiconductor memory device comprising: a select gate arranged in a first region on a substrate;a storage node arranged in a second region neighboring to said first region;a first diffusion region provided in a third region neighboring to said second region;a control gate arranged on said storage node; anda driving circuit that controls voltages applied to said substrate, said select gate, said first diffusion region and said control gate; whereinsaid driving circuit exercises control so that, during an erasure operation, two of three voltages, that is, a voltage applied to said substrate or said first diffusion region, a voltage applied to said select gate and a voltage applied to said control gate, will be negative, and the remaining voltage will be positive.

2. The semiconductor memory device according to claim 1 wherein said driving circuit exercises control so that, during the erasure operation, the voltages of said select gate and said control gate will be negative, and the voltage of said substrate or said first diffusion region will be positive.

3. The semiconductor memory device according to claim 1 wherein said driving circuit exercises control so that, during the erasure operation, the voltage of said substrate or said first diffusion region and the voltage of said control gate will be negative and the voltage of said select gate will be positive.

4. The semiconductor memory device according to claim 1 wherein said driving circuit exercises control so that, during the erasure operation, the voltage of said select gate and the voltage of said substrate or said first diffusion region will be negative, and the voltage of said control gate will be positive.

5. The semiconductor memory device according to claim 1 wherein, during said erasure operation, a voltage of the same polarity as that of the voltage applied to said substrate is applied by said driving circuit to said first diffusion region.

6. The semiconductor memory device according to claim 2 wherein, during said erasure operation, a voltage of the same polarity as that of the voltage applied to said substrate is applied by said driving circuit to said first diffusion region.

7. The semiconductor memory device according to claim 3 wherein, during said erasure operation, a voltage of the same polarity as that of the voltage applied to said substrate is applied by said driving circuit to said first diffusion region.

8. The semiconductor memory device according to claim 4 wherein, during said erasure operation, a voltage of the same polarity as that of the voltage applied to said substrate is applied by said driving circuit to said first diffusion region.