This invention relates to a semiconductor memory device and, more particularly, to a programmable non-volatile semiconductor memory device.
Among known non-volatile semiconductor memory devices, there is such a one shown in
The first diffusion regions 107 extend in one direction on the surface of a substrate 101 and are separated one from another. The first diffusion regions 107 are used as local bitlines (LB). The select gates (SG) 103 are arranged in regions on the substrate sandwiched between neighboring ones of the first diffusion regions 107, with the interposition of a plural number of insulating films 102, and are extended along the extending directions of the first diffusion regions 107. The floating gates (FG) 106 are storage nodes and are arranged in regions defined between the first diffusion regions 107 and the select gates 103, with the interposition of the insulating films 102. When seen in a plan view, the floating gates look like islands. The control gates (CG) 111 are arranged on the top of the floating gates 106 and the select gates 103, with the interposition of a plural number of insulating films 108. The control gates 111 are arranged in juxtaposition, with an interval from one another, and are extended in a direction of crossing the select gates 103. The control gates 111 are used as wordlines.
One 107 out of the first diffusion regions 107, lying on either sides of the select gate 103, the floating gate 106, the control gate 111 and the select gate 103 make up a first unit cell. The other 107 of the first diffusion regions 107, lying on either sides of the select gate 103, the floating gate 106, the control gate 111 and the select gate 103, make up a second unit cell. The first diffusion region 107 is shared by a plural number of unit cells. With this non-volatile semiconductor memory device, an inversion layer 120 is formed on the surface of the substrate 101 below the select gate 103 in the cell region.
The voltages applied to the first diffusion region 107, select gate 103, control gate 111 and to the substrate 101 (well 101a) is controlled by a driving circuit, not shown, constituting a portion of a peripheral circuit in the semiconductor memory device.
The erasure operation by the non-volatile semiconductor memory device, according to the related art 1, is described as follows.
Referring to
where Q denotes the quantity of electricity of the floating gate 106, Ccf denotes the capacitance between the control gate 111 and the floating gate 106, Cfsub denotes the capacitance between the floating gate 106 and the substrate 101, and Csf denotes the capacitance between the select gate 103 and the floating gate 106.
Referring to
where Q denotes the quantity of electricity of the floating gate 106, Ccf denotes the capacitance between the control gate 111 and the floating gate 106, Cfsub denotes the capacitance between the floating gate 106 and the substrate 101, and Csf denotes the capacitance between the select gate 103 and the floating gate 106.
[Patent document 1] JP Patent Kokai Publication No. JP-P2005-51227A
The disclosure of the Patent document 1 is herein incorporated by reference thereto.
However, with the erasure operation according to the related art 1, shown in
It is a principal object of the present invention to provide a semiconductor memory device in which an erasure operation may be carried out at a lower voltage.
According to the present invention, there is provided a semiconductor memory device including a select gate arranged in a first region on a substrate; a storage node arranged in a second region neighboring to the first region; a first diffusion region provided in a third region neighboring to the second region; a control gate arranged on the storage node; and a driving circuit that controls a voltages applied to the substrate, select gate, first diffusion region and control gate. The driving circuit performs control so that, during an erasure operation, two of three voltages, that is, a voltage applied to the substrate or the first diffusion region, a voltage applied to the select gate and a voltage applied to the control gate, will be negative, and the remaining voltage will be positive.
According to a second mode, the driving circuit may exercise control so that, during the erasure operation, the voltages of the select gate and the control gate will be negative, and the voltage of the substrate or the first diffusion region will be positive.
According to a third mode, the driving circuit may exercise control so that, during the erasure operation, the voltage of the substrate or the first diffusion region and the voltage of the control gate will be negative and the voltage of the select gate will be positive.
According to a fourth mode, the driving circuit may exercise control so that, during the erasure operation, the voltage of the select gate and the voltage of the substrate or the first diffusion region will be negative, and the voltage of the control gate will be positive.
According to a fifth mode, during the erasure operation, a voltage of the same polarity as that of the voltage applied to the substrate may be applied by the driving circuit to the first diffusion region.
The meritorious effects of the present invention are summarized as follows.
According to the present invention, set forth in modes 1 to 5, it is possible to use lower voltages as the voltages applied to the select gate, substrate (well) and control gate at the time of electron extraction by tunneling from the storage node. The peripheral circuit may be reduced in size as a result of lowering the voltages applied. The reason is that a voltage and an electrical field such that electrons may be extracted to the substrate side under a lower applied voltage can be generated by three capacitive couplings, namely a capacitive coupling between the control gate and the storage node, a capacitive coupling between the select gate and the storage node and a capacitive coupling between the substrate (well) or the first diffusion region and the storage node. On the other hand, the erasure operation may be increased in speed by increasing the voltages applied to the select gate, to the substrate (well) or the first diffusion region, or to the control gate.
A semiconductor memory device according to a first example of the present invention will now be described with reference to the drawings.
The semiconductor memory device according to the first example is a non-volatile semiconductor memory device for storing the 2-bit information per cell. The semiconductor memory device includes a substrate 1, an insulating film 2, a select gate 3, an insulating film 4, an insulating film 5, a floating gate 6, a first diffusion region 7, an insulating film 8, an insulating film 9, a control gate 11, a second diffusion region 21 (
The substrate 1 is a P-type silicon substrate. The substrate 1 includes a well 1a below the select gate 3 and the floating gate 6. The well 1a is a p−type diffusion region. The well 1a is also termed a “common source diffusion region”.
In the substrate 1, a channel constituting a path interconnecting the first diffusion region 7 and the second diffusion region 21 includes a first path section L and a second path section S, when the substrate 1 is viewed from above. The first path section L is formed by extending from one of the second diffusion regions 21 along a first direction as defined in association with the planar shape of the select gate 3. The end of the first path section L, extending from the second diffusion region 21, is bent to form the second path section S extending as far as the first diffusion region 7 along a second direction forming a preset angle, such as a right angle, with respect to the first direction. A channel of the first path section L below the select gate 3 within the cell region becomes an inversion layer 20 when the positive voltage is applied to the select gate 3. In the second path section S, the region below the floating gate 6 also is used as a channel region. In the similar manner, a channel region constituting a path interconnecting the first diffusion region 7 and the second diffusion region 21 includes a first path section and a second path section, when the substrate 1 is viewed from above. The first path section L is formed by extending from one of the second diffusion regions 21 along the longitudinal direction of the select gate 3. The end of the first path section, extending from the second diffusion region 21, is bent at a preset angle, such as a right angle, with respect to the first direction, in order to form the second path section extending as far as the first diffusion region 7.
The insulating film 2 is provided between the select gate 3 and the substrate 1. The insulating film 2 may be formed by, for example a silicon oxide film, and is sometimes referred to herein as a select gate insulating film.
The select gate (SG) 3 is an electrically conductive film provided on the insulating film 2. As the material for the select gate 3, polysilicon, for example, may be used. The select gate 3 includes a pair of select gate sections SG0 and SG1 in one erasure block 23 (see
The insulating film 4 is provided on the silicon gate 3 (
The insulating film 5 is formed on a sidewall section of the insulating film 4, on a sidewall section of the select gate 3, on a sidewall section of the insulating film 2, and between the substrate 1 and the floating gate 6. The insulating film 5 may, for example, be a silicon oxide film (
The floating gate 6 functions as a storage node, and is provided, via insulating film 5, on both sides of a select gate structure formed by a stack of the select gate 3 and the insulating film 4 (
The first diffusion region 7 is an n+ diffusion area, formed in a predetermined region (a region between neighboring floating gates 6) of the substrate 1, and is arranged along a direction of extension of the select gates 3, more specifically, the combs of the select gates (
The insulating film 8 is disposed between the floating gate 6 and the control gate (CG) 11, and may further extend over the insulating film 4 (
The insulating film 9 is provided between the insulating film 8 and the first diffusion region 7 (
The control gate 11 is extended in a direction perpendicular to the longitudinal direction of the select gate 3, and crosses the select gate 3 with an overpass (
The second diffusion region 21 is an n+ diffusion region and becomes a source/drain region of a cell transistor (
A driving circuit 22 is part of a peripheral circuit, and controls the voltages applied to the first diffusion region 7, select gate 3, control gate 11, substrate 1 (well 1a) and to the second diffusion region 21. It is noted that the voltage control by the driving circuit 22 differs, at least in its erasure operation, from the voltage control by the driving circuit of the non-volatile semiconductor memory device according to the related art 1. The voltage control in the erasure operation by the driving circuit 22 will be explained subsequently.
The semiconductor memory device of the first example is similar in constitution to the non-volatile semiconductor memory device according to the related art 1, except for the driving circuit 22. Also, the semiconductor memory device of the first example may be fabricated by a method which is similar in the fabrication process from the stage of forming the well 1a up to the stage of forming the control gate 11 to the method for fabricating the non-volatile semiconductor memory device according to the related art 1. In this connection, the reference is made to the disclosure of Patent document 1 which is incorporated herein by reference thereto.
The operation for erasure of the semiconductor memory device according to the first example will now be described with reference to the drawings.
Referring to
Referring to
Referring to
The electrical state of the floating gate 6 during the first to third erasure operations is as shown in
where Q is the quantity of electricity of the floating gate 6, Ccf is the capacitance across the control gate 11 and the floating gate 6, Cfsub is the capacitance across the floating gate 6 and the substrate 1, and Csf is the capacitance across the select gate 3 and the floating gate 6.
According to the first example, it is possible to use lower voltages as the voltages applied to the select gate 3, the voltage applied to the substrate 1 (well 1a) or the first diffusion region 7, or the voltage applied to the control gate 11, upon extracting electrons from the floating gate 6. By using lower voltages, it becomes possible to reduce the size of the peripheral circuit. The reason is that, by three capacitive couplings, namely the capacitive coupling between the control gate 11 and the floating gate 6, the capacitive coupling between the select gate 3 and the floating gate 6 and the capacitive coupling between the substrate 1 (well 1a) or the first diffusion region 7 and the floating gate 6, it is possible to generate a voltage and electrical field such that electrons e may be extracted towards the substrate at a lower applied voltage(s). Moreover, the erasure operation can be raised in speed if the voltage applied to the control gate 11 is increased.
It should be noted that other objects, features and aspects of the present invention will become apparent in the entire disclosure and that modifications may be done without departing the gist and scope of the present invention as disclosed herein and claimed as appended herewith.
Also it should be noted that any combination of the disclosed and/or claimed elements, matters and/or items may fall under the modifications aforementioned.
Number | Date | Country | Kind |
---|---|---|---|
2006-032558 | Feb 2006 | JP | national |
Number | Name | Date | Kind |
---|---|---|---|
6493262 | Wald et al. | Dec 2002 | B1 |
20020008277 | Chen | Jan 2002 | A1 |
20020019097 | Arai et al. | Feb 2002 | A1 |
20030071301 | Wald et al. | Apr 2003 | A1 |
20050029577 | Nishizaka et al. | Feb 2005 | A1 |
20060083066 | Hasegawa et al. | Apr 2006 | A1 |
Number | Date | Country |
---|---|---|
2005-51227 | Feb 2005 | JP |
Number | Date | Country | |
---|---|---|---|
20070183222 A1 | Aug 2007 | US |