Number | Date | Country | Kind |
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5-215869 | Aug 1993 | JPX |
Number | Name | Date | Kind |
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5324975 | Kumagai et al. | Jun 1994 |
Number | Date | Country |
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4-279055 | Oct 1992 | JPX |
5-29579 | Feb 1993 | JPX |
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"A 1.28 .mu.m.sup.2 Bit-Line Shielded Memory Cell Technology for 64 Mb DRAMS", Kawamoto et al., 1990 Symposium on VLSI Technology, pp. 13-14. |
"Bidirectional Matched Global Bit Line Scheme for High Density DRAMS", Ahn et al., VLSI Circuit 1993, pp. 91-92. |