Claims
- 1. A method of manufacturing a semiconductor memory having memory cells, each composed of a transistor and a capacitor formed on a semiconductor substrate, the method comprising the steps of:
- forming a gate electrode on a gate insulation film in each memory cell region where said memory cells are to be formed on the semiconductor substrate;
- forming source and drain regions in the memory cell region by doping the semiconductor substrate with impurities, using the gate electrode as a mask;
- forming a bit line for the memory cell region and connecting the bit line to one of the source and drain regions;
- forming pad electrodes for the memory cell region, for connecting the bit line with one of the source and drain regions of the transistor and for connecting the electrode with the other of the source and drain regions of the transistor, wherein said pad electrode for connecting the bit line with one of the source and drain regions of the transistor is formed so as to be separated from the memory cell region;
- forming a first capacitor electrode for the memory cell region above the bit line and connecting the first capacitor electrode to the other of the source and drain regions which is not connected to the bit line; and
- forming a second capacitor electrode for the memory cell region on an insulation film formed on the first capacitor electrode.
- 2. The method as claimed in claim 1, wherein the bit line is disposed on an element separating region between memory cell regions, and the bit line extends orthogonally to a word line, which word line is composed of a gate electrode of the transistor.
- 3. The method as claimed in claim 1, wherein said transistor is a MOS transistor, and said capacitor is a MOS capacitor.
- 4. The method as claimed in claim 3, wherein one of source and drain regions of the MOS transistor contacts the bit line.
- 5. The method as claimed in claim 3, wherein the bit line is disposed on a memory cell region and orthogonally to a word line which is composed of a gate electrode of the MOS transistor.
- 6. The method as claimed in claim 1, wherein opposite surfaces of said first and second capacitor electrodes are formed unevenly in order to increase the interfacial area therebetween with the intervention of said insulation film.
- 7. The method as claimed in claim 6, wherein grooves are formed in said first and second capacitor electrodes.
- 8. The method as claimed in claim 1, further comprising the step of separating each adjacent memory cell by forming a groove therebetween and filling said groove with an insulating material.
- 9. The method as claimed in claim 8, wherein said insulating material is silicon oxide.
- 10. The method as claimed in claim 8, wherein said insulating material is a non-doped polycrystalline silicon.
Priority Claims (1)
Number |
Date |
Country |
Kind |
63-069626 |
Mar 1988 |
JPX |
|
Parent Case Info
This application is a divisional of application Ser. No. 07/831,657,filed Feb. 7, 1992, now U.S. Pat. No. 5,234,199, which is a continuation of application Ser. No. 07/328,374, filed Mar. 24, 1989, now abandoned.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4816423 |
Havemann |
Mar 1989 |
|
4970564 |
Kimura et al. |
Nov 1990 |
|
5055420 |
Ikeda et al. |
Oct 1991 |
|
Non-Patent Literature Citations (1)
Entry |
Kinney et al., "A Non-Volatile Memory Cell Based on Ferroelectric Storage Capacitors", IEDM (1987), pp. 850-851. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
831657 |
Feb 1992 |
|
Continuations (1)
|
Number |
Date |
Country |
Parent |
328374 |
Mar 1989 |
|