Patent Application
20090309190
The present invention relates to improvements in semiconductor processing. Embodiments of the invention relate to the manufacture of a semiconductor device in a SOI (Silicon On Insulator) layer in which gettering sites are provided.
Several techniques are known to provide gettering sites in silicon substrates on which semiconductor devices are fabricated. These gettering sites are provided in order to trap impurities such as metals diffusing from outside into the silicon, for example during high-temperature processing, which can deteriorate the performance of the fabricated devices. The methods include intrinsic gettering, in which thermal treatments are used to create both a defect-free zone at the surface of the substrate wafers, where the devices are formed, and a deeper defective bulk area where impurities are gettered. Other techniques include extrinsic gettering by providing a highly doped polysilicon layer on the back surface of the wafer or by creating mechanical damage on the back surface. Alternatively, a lightly doped epitaxial layer formed on a heavily doped substrate will provide gettering by segregation at the epitaxy-substrate interface.
In bonded SOI wafers, however, these kinds of gettering techniques are not efficient because the buried oxide layer prevents the diffusion of most types of impurity out of the active silicon region into the bulk of the wafer where the gettering sites are normally formed. Therefore, the impurities remain in the SOI region and degrade devices grown using standard semiconductor device manufacturing methods. One technique to overcome this is to provide a highly doped implanted layer in the top surface of the SOI wafer, close to the devices, which will then getter impurities away from these devices. Another technique is to provide trenches around devices which can getter impurities through mechanically-induced or stress-induced defect generation in the silicon material. However, both these methods have the disadvantage that substantial extra area is needed in the device layouts to accommodate the added features, while more complex and expensive processing is also necessary.
Preferred embodiments of the present invention aim to address the disadvantages encountered with the above techniques.
Aspects of the invention are set out in the independent claims.
Preferred embodiments of the invention provide gettering sites within the SOI layer, formed during fabrication of the SOI substrate, thus enabling the efficient gettering of impurities diffusing into the SOI layer without any additional area or processing requirements for the chips.
Embodiments of the present invention provide a layer with implanted (or otherwise inserted) Ge (germanium) atoms. These are implanted (or otherwise inserted) into the surface of the device wafer before bonding to the handle, and form a gettering region in the SOI near the interface of the SOI with the buried oxide, when fabrication of the SOI is completed. The Ge sites have the ability to getter impurities diffusing through the SOI layer and trap them throughout the semiconductor processing sequence, thus enabling high quality semiconductor devices to be fabricated.
Some preferred embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings, in which:
A first embodiment of the present invention will now be described with reference to
A handle wafer 50 is also provided. The handle wafer 50 is polished and oxidised so that an oxide layer 60 is formed at its surface. Next, the device wafer 10 is fusion bonded to the oxidised polished handle wafer 50. The device wafer 10 is bonded to the handle wafer 50 such that surface 15 of the device wafer 10 is closest to handle wafer 50. The bonded device and handle wafers thus form a bonded pair 70. A bond anneal may be carried out. The device wafer 10 is then thinned from the back to the required thickness. Those portions of oxide layer 60 which are located at the surface of the bonded wafer pair 70 are also removed so that only a buried oxide layer 100 remains between the handle wafer 50 and surface 15 of device wafer 10. Thus the device wafer 10 located on the buried oxide layer 100 forms a SOI wafer. The wafer contains Ge atoms in the SOI layer 80, just above the buried oxide 100, where gettering sites have been formed. Next, semiconductor devices are fabricated in the SOI layer 80, for example using trench isolation (as indicated by vertical lines 90) in combination with integrated circuit processing, and gettering takes place either through a chemical interaction between impurities and the Ge atoms or by physical interaction between impurities and damage in the silicon caused by the implantation process. Thus, high-quality devices can be formed using standard semiconductor processes.
It will be understood that the gettering sites form isolated islands in the silicon material, i.e. no substantially continuous Ge or SiGe layer is formed. The maximum extent of most (e.g. 95%), preferably of all, isolated islands in any direction is preferably less than 50 nm, more preferably less than 30 nm and most preferably less than 10 nm.
In an alternative embodiment, which generally follows the same sequence as the first embodiment, the oxide layer 20 on device wafer 10 is not stripped before the joining of the device wafer 10 to handle wafer 50. In this case the handle wafer 50 may be either oxidised or unoxidised.
In a third embodiment, which again generally follows the sequence of the first embodiment, the screen oxide layer 20 is stripped, but another oxide layer is formed on the device wafer 10 prior to joining to handle wafer 50. Again, in this case handle wafer 50 may be oxidised or unoxidised.
In each of the above embodiments, the Ge could be inserted into the silicon by other means, for example by gaseous diffusion of Ge atoms.
Examples of results of the invention are shown in
“Epi” means standard epitaxial substrate, i.e. not SOI. This is expected to give a good oxide since internal gettering can occur. This material is therefore used as a quality benchmark.
“XFab FZ” and “XFab CZ” are unimplanted SOI samples produced by X-Fab Semiconductor Foundries AG, whereby “FZ” and “CZ” refer to the handle silicon material type (Float Zone or Czochralski). “Comm.p.” stands for a commercially available unimplanted SOI produced by a third party.
The oxides for SOI with implanted layers show excellent quality and yield, while those on standard SOI have poor yields. By way of explanation, each symbol represents a measurement point taken at certain standard positions across a wafer. Symbols at about 40 V means that the oxides have broken down electrically at about 40 V applied bias for these positions, which indicates good quality. Those at −100V show points which have broken down at low voltages and so indicate poor oxide in these positions. The wafers have varying amounts of good and bad points, depending on the wafer yield, e.g. Ge is 100% good, while XFab FZ has only about 50% of the measurement points good.
From a synopsis of
Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 0609278.7 | May 2006 | GB | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/GB2007/050255 | 5/11/2007 | WO | 00 | 3/13/2009 |
