SEMICONDUCTOR STORAGE ELEMENT AND MANUFACTURING METHOD THEREOF

Abstract

A semiconductor storage element according to the present embodiment includes a laminated body, a semiconductor layer, a first insulator, a second insulator, a third insulator, and a fourth insulator. In the laminated body, the insulating layers and conductive layers are alternately laminated in a first direction. The third insulator is disposed between the laminated body and the second insulator. A first part of the fourth insulator is disposed between each of the conductive layers and the third insulator. The average concentration of heavy hydrogen in the first part is higher than the average concentration of heavy hydrogen in the third insulator. The ratio of heavy hydrogen concentration to light hydrogen concentration in the first part is smaller than the ratio of heavy hydrogen concentration to light hydrogen concentration in the third insulator.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2022-203628, filed on Dec. 20, 2022, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments of the present invention relate to a semiconductor storage element and a manufacturing method thereof.

BACKGROUND

A NAND flash memory in which memory cells are three-dimensionally disposed is known as a semiconductor storage device. In the NAND flash memory, a laminated body in which a plurality of electrode layers and insulating layers are alternately laminated is provided with a memory hole penetrating through the laminated body. A block insulator, an electric charge accumulation film, a tunnel insulator, and a semiconductor layer (channel layer) are provided in the memory hole to form a memory string in which a plurality of memory cells are connected in series. Data is stored in the memory cells by controlling the amount of electric charge held in the electric charge accumulation film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view illustrating the structure of a semiconductor storage element of a first embodiment;

FIG. 2 is a cross-sectional view illustrating a method of manufacturing the semiconductor storage element of the first embodiment;

FIG. 3 is a cross-sectional view illustrating the method of manufacturing the semiconductor storage element of the first embodiment;

FIG. 4 is a cross-sectional view illustrating the method of manufacturing the semiconductor storage element of the first embodiment;

FIG. 5 is a cross-sectional view illustrating the method of manufacturing the semiconductor storage element of the first embodiment;

FIG. 6 is a cross-sectional view for description of thermal treatment in the method of manufacturing the semiconductor storage element of the first embodiment;

FIG. 7 is a cross-sectional view for description of the thermal treatment in the method of manufacturing the semiconductor storage element of the first embodiment;

FIG. 8 is a graph illustrating distribution of heavy hydrogen introduced into a cell multilayer film through the thermal treatment illustrated in FIG. 7;

FIG. 9 is a graph illustrating distribution of the concentration ratio of heavy hydrogen concentration to light hydrogen concentration in the cell multilayer film;

FIG. 10 is a cross-sectional view illustrating the method of manufacturing the semiconductor storage element of the first embodiment;

FIG. 11 is a cross-sectional view illustrating a method of manufacturing a semiconductor storage element of a second embodiment;

FIG. 12 is a cross-sectional view illustrating the method of manufacturing the semiconductor storage element of the second embodiment;

FIG. 13 is a cross-sectional view illustrating the method of manufacturing the semiconductor storage element of the second embodiment;

FIG. 14 is a cross-sectional view illustrating the method of manufacturing the semiconductor storage element of the second embodiment;

FIG. 15 is a cross-sectional view illustrating the method of manufacturing the semiconductor storage element of the second embodiment;

FIG. 16 is a cross-sectional view illustrating the method of manufacturing the semiconductor storage element of the second embodiment;

FIG. 17 is a cross-sectional view illustrating the method of manufacturing the semiconductor storage element of the second embodiment;

FIG. 18 is a cross-sectional view illustrating the method of manufacturing the semiconductor storage element of the second embodiment;

FIG. 19 is a cross-sectional view illustrating the method of manufacturing the semiconductor storage element of the second embodiment; and

FIG. 20 is a cross-sectional view illustrating the method of manufacturing the semiconductor storage element of the second embodiment.

DETAILED DESCRIPTION

Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments. It should be noted that the drawings are schematic or conceptual, and the relationship between the thickness and the width in each element and the ratio among the dimensions of elements do not necessarily match the actual ones. Even if two or more drawings show the same portion, the dimensions and the ratio of the portion may differ in each drawing. In the present specification and the drawings, elements identical to those described in the foregoing drawings are denoted by like reference characters and detailed explanations thereof are omitted as appropriate.

A semiconductor storage element according to the present embodiment includes a laminated body, a semiconductor layer, a first insulator, a second insulator, a third insulator, and a fourth insulator. In the laminated body, the insulating layers and conductive layers are alternately laminated in a first direction. The semiconductor layer is disposed in a first direction in the laminated body. The first insulator is disposed in the first direction between the laminated body and the semiconductor layer. The second insulator is disposed in the first direction between the laminated body and the first insulator. The third insulator is disposed in the first direction between the laminated body and the second insulator. The fourth insulator includes a first part and a second part. The first part is disposed between each of the conductive layers and the third insulator, and the second part is disposed in a second direction intersecting the first direction between each of the conductive layers and the insulating layer and is connected to the first part. The average concentration of heavy hydrogen in the first part is higher than the average concentration of heavy hydrogen in the third insulator. The ratio of heavy hydrogen concentration to light hydrogen concentration in the first part is smaller than the ratio of heavy hydrogen concentration to light hydrogen concentration in the third insulator.

First Embodiment

FIG. 1 is a perspective view illustrating the structure of a semiconductor storage element of a first embodiment. The semiconductor storage element in FIG. 1 is, for example, a three-dimensional NAND memory.

The semiconductor storage element in FIG. 1 includes a core insulator 1, a channel semiconductor layer 2, a tunnel insulator 3, an electric charge accumulation film 4, a block insulator 5, and an electrode layer 6. The block insulator 5 includes an insulator 5a and an insulator 5b. The electrode layer 6 includes a barrier metal layer 6a and an electrode material layer 6b. The tunnel insulator 3, the electric charge accumulation film 4, and the block insulator 5 are also referred to as a cell multilayer film.

In the semiconductor storage element of the present embodiment, a plurality of electrode layers and a plurality of insulating layers are alternately laminated on a substrate, and a memory hole H1 is provided in the electrode layers and the insulating layers. FIG. 1 illustrates the electrode layer 6 as one of the electrode layers. The electrode layers function as, for example, word lines of a NAND memory. FIG. 1 illustrates an X direction and a Y direction parallel to the surface of the substrate and orthogonal to each other, and a Z direction orthogonal to the surface of the substrate. In the present specification, the positive Z direction is treated as the upward direction, and the negative Z direction is treated as the downward direction. The negative Z direction may be or may not be aligned with the direction of gravity.

The core insulator 1, the channel semiconductor layer 2, the tunnel insulator 3, the electric charge accumulation film 4, and the insulator 5a are formed in the memory hole H1 and constitute a memory cell of a NAND memory. The insulator 5a is formed on the surfaces of the electrode layers and the insulating layers in the memory hole H1, and the electric charge accumulation film 4 is formed on the surface of the insulator 5a. The electric charge accumulation film 4 can accumulate electric charge between an outer side surface and an inner side surface. The tunnel insulator 3 is formed on the surface of the electric charge accumulation film 4, and the channel semiconductor layer 2 is formed on the surface of the tunnel insulator 3. The channel semiconductor layer 2 functions as a channel of the memory cell. The core insulator 1 is formed in the channel semiconductor layer 2.

The insulator 5a is, for example, a SiO film (silicon oxide film). The electric charge accumulation film 4 is, for example, a SiN film (silicon nitride film). The tunnel insulator 3 is, for example, a SiON film (silicon oxynitride film). The channel semiconductor layer 2 is, for example, a polysilicon layer. The core insulator 1 is, for example, a silicon oxide film.

The insulator 5b, the barrier metal layer 6a, and the electrode material layer 6b are formed between insulating layers adjacent to each other and sequentially formed on the lower surface of the upper insulating layer, the upper surface of the lower insulating layer, and the side surface of the insulator 5a. The insulator 5b is, for example, a metal insulator made of aluminum oxide or the like. The barrier metal layer 6a is, for example, a titanium nitride film. The electrode material layer 6b is, for example, a W (tungsten) layer.

FIGS. 2 to 5 and 10 are cross-sectional views illustrating a method of manufacturing the semiconductor storage element of the first embodiment.

First, an insulator 12 is formed above a substrate 11, and a plurality of sacrifice layers 13 and a plurality of insulating layers 14 are alternately formed on the insulator 12 (FIG. 2). As a result, a multilayer film S1 alternately including the plurality of sacrifice layers 13 and the plurality of insulating layers 14 is formed on the insulator 12. The substrate 11 is, for example, a semiconductor substrate such as a silicon substrate. The insulator 12 is, for example, a silicon oxide film (SiO). Each sacrifice layer 13 is, for example, a silicon nitride film (SiN), and each insulating layer 14 is, for example, a silicon oxide film (SiO).

Subsequently, the memory hole H1 penetrating through the multilayer film S1 and the insulator 12 is formed (FIG. 2). As a result, the upper surface of a layer provided between the substrate 11 and the insulator 12 is exposed in the memory hole H1. Details of the layer will be described later.

Subsequently, the insulator 5a, the electric charge accumulation film 4, the tunnel insulator 3, and part of the channel semiconductor layer 2 are sequentially formed in the memory hole H1 (FIG. 3). Subsequently, the insulator 5a, the electric charge accumulation film 4, the tunnel insulator 3, and the part of the channel semiconductor layer 2 are removed from a bottom part of the memory hole H1 by etching, and then, the rest of the channel semiconductor layer 2 and the core insulator 1 are sequentially formed in the memory hole H1 (FIG. 3). As a result, the insulator 5a, the electric charge accumulation film 4, the tunnel insulator 3, the channel semiconductor layer 2, and the core insulator 1 are sequentially formed on the side surfaces of the multilayer film S1 and the insulator 12 in the memory hole H1.

Subsequently, a slit (not illustrated) is formed in the multilayer film S1 and used to remove the sacrifice layers 13 with liquid chemical such as phosphoric acid. As a result, a plurality of hollow spaces H2 are formed between the insulating layers 14 (FIG. 4).

Subsequently, the insulator 5b containing aluminum oxide is formed on the surfaces of the insulating layers 14 and the insulator 5a in the hollow spaces H2 (FIG. 5). As a result, the block insulator 5 including the insulator 5a and the insulator 5b is formed.

Subsequently, radical oxidation (radical reforming) is performed as illustrated in FIG. 6. The radical oxidation is performed in a heating furnace or an RTP by using OH* or OD* and using oxygen radical (O*). A thermal treatment atmosphere has a temperature in the range of 800° C. to 1100° C. The oxygen radical (O*) may be formed from oxygen (O₂) gas by using a plasma generation mechanism.

The radical oxidation is performed under conditions of, for example, 900° C. and 30 seconds.

Through the radical oxidation, a large number of trap levels (trap sites) T are formed in the insulators 5a and 5b. FIG. 6 omits illustrations of trap levels T included in the electric charge accumulation film 4 and the tunnel insulator 3.

Subsequently, rapid thermal processing (RTP) is performed under a thermal load condition of, for example, 1000° C. or higher by using heavy hydrogen (D₂) gas and heavy water (D₂O). Accordingly, crystallization and film quality improvement of the insulator 5b containing aluminum oxide (AlO) are performed, and heavy hydrogen (D) is introduced into the cell multilayer film, for example, the block insulator 5, the electric charge accumulation film 4, and the tunnel insulator 3 as illustrated in FIG. 7. FIG. 7 is a cross-sectional view illustrating the process of heavy hydrogen (D) introduction in one hollow space H2.

The RTP using heavy hydrogen (D₂) gas and heavy water (D₂O) is performed under conditions of, for example, 1035° C. and 0 to 10 seconds approximately. The heavy water (D₂O) is introduced in a liquid state into an RTP device.

An RTP using heavy water (D₂O) may be performed without using heavy hydrogen (D₂) gas. In the RTP using heavy water (D₂O), argon (Ar) or nitrogen (N₂) gas may be contained as carrier gas. When argon or nitrogen is used, heavy hydrogen (D₂) gas, which is expensive, is not used, and moreover, even with a small amount of heavy water (D₂O), heavy hydrogen (D) can be sufficiently introduced into the insulator because heavy water (D₂O) highly efficiently replaces light hydrogen (H) in an insulator with heavy hydrogen (D). Thus, a heavy hydrogen (D) introduction process with excellent productivity can be provided.

As illustrated in FIG. 7, a dangling bond of each trap level T formed through the process in FIG. 6 is terminated with heavy hydrogen (D). Thus, a larger amount of heavy hydrogen (D) can be introduced into the insulators 5a and 5b.

FIG. 8 illustrates concentration distribution in the depth direction after the heavy hydrogen (D) introduction. The horizontal axis represents depth from the insulator 5b containing AlO in the X direction, in other words, distance in the X direction. Specifically, the horizontal axis represents distance in the depth direction from the surface of the insulator 5b containing AlO to each of the insulator 5b, the insulator 5a containing SiO, the electric charge accumulation film 4 containing SiN, the tunnel insulator 3 containing SiON, and the channel semiconductor layer 2. The vertical axis represents the concentration of heavy hydrogen (D).

As understood from the first embodiment in FIG. 8, heavy hydrogen (D) is mainly introduced into the electric charge accumulation film 4 containing SiN and the tunnel insulator 3 containing SiON. The average concentration of heavy hydrogen (D) in the cell multilayer film decreases in the following order:

the electric charge accumulation film 4>the tunnel insulator 3>the insulator 5b>the insulator 5a.

In other words, the average concentration of heavy hydrogen (D) in the cell multilayer film decreases in the order of the electric charge accumulation film 4, the interface between the electric charge accumulation film 4 and the tunnel insulator 3, and the tunnel insulator 3. The average concentration of each film is a value obtained by integrating concentration distribution in the depth direction of the film and dividing the integrated value by the thickness (thickness in the X direction) of the film. The boundary between the electric charge accumulation film 4 containing SiN and the tunnel insulator 3 containing SiON can be determined based on SiN intensity and O intensity analysis curve in secondary ion mass spectrometry (SIMS) analysis.

As described above, the average concentration of heavy hydrogen (D) in the insulator 5b is higher than the average concentration of heavy hydrogen (D) in the insulator 5a.

FIG. 9 illustrates distribution of the concentration ratio of the concentration of heavy hydrogen (D) to the concentration of light hydrogen (H). The horizontal axis represents, as in the horizontal axis of the graph illustrated in FIG. 8, the depth of the insulator 5b containing AlO in the X direction, in other words, the distance of the insulator 5b in the X direction. The vertical axis represents the concentration ratio (D/H concentration ratio) of the concentration of heavy hydrogen (D) to the concentration of light hydrogen (H).

As understood from FIG. 9, distribution of the D/H concentration ratio from the electric charge accumulation film 4 to the channel semiconductor layer 2 has a tendency similar to that for distribution of the concentration of heavy hydrogen (D) illustrated in FIG. 8. However, the D/H concentration ratio in the insulator 5b is smaller than the D/H concentration ratio in the insulator 5a. The D/H concentration ratio in the insulator 5a is equal to or larger than 100 in some cases.

Through the process described above with reference to FIGS. 6 and 7, the concentration of heavy hydrogen (D) and the D/H concentration ratio in the insulators 5a and 5b can be made high. Accordingly, a larger number of dangling bonds in the insulators 5a and 5b can be terminated with heavy hydrogen (D). Moreover, light hydrogen (H) termination with low reliability can be reduced. As a result, leakage of electric charge from the electric charge accumulation film 4 to the block insulator 5 can be reduced. Thus, the data holding characteristic and the cycle resistance can be improved, and the reliability of the memory cell can be improved.

As illustrated in FIG. 9, the D/H concentration ratio in at least one of part of the insulator 5b, which is along the insulator 5a, and the insulator 5a is equal to or larger than one. More preferably, the D/H concentration ratio in at least one of the part of the insulator 5b, which is along the insulator 5a, and the insulator 5a is equal to or larger than 10. In a case where a dangling bond, which would be a defect in an insulator, is terminated with light hydrogen (H), light hydrogen (H) is eliminated with electric stress and the electric charge holding characteristic as a storage element and the resistance as an insulator degrade due to the defect. In a case where a dangling bond in an insulator is terminated with heavy hydrogen (D), heavy hydrogen (D) is stable against electric stress and unlikely to be eliminated. As a result, a dangling bond, which would be a defect, is stably terminated with heavy hydrogen (D) and the electric charge holding characteristic as a storage element and the resistance as an insulator significantly improve. The reliability of the memory cell can be significantly improved by not only introducing heavy hydrogen (D) but also reducing light hydrogen (H) to achieve the D/H concentration ratio of 10 or larger. In a case where the D/H concentration ratio is equal to or larger than 10, the fraction of dangling bonds terminated with heavy hydrogen (D) exceeds D/(D+H) or 10/(10+1)=90.9%. The characteristics of a semiconductor element can be significantly improved when the fraction of heavy hydrogen (D) termination in an insulator exceeds 90.9%.

A high dielectric insulator (High-k film) is used as the part of the insulator 5b, which is along the insulator 5a. Typically, when an insulator having a high dielectric constant k is used as a gate insulator, gate capacitance can be increased with a small thickness and the reliability of a semiconductor can be improved. However, a material with a high dielectric constant k typically tends to have small bandgap energy. Accordingly, electric charge accumulated in the electric charge accumulation film 4 is likely to leak through the part of the insulator 5b, which is along the insulator 5a, and the insulator 5a, and the electric charge holding characteristic is to degrade. Thus, the characteristics of a semiconductor element improve when the D/H concentration ratio in the High-k insulator is set to one or larger. The D/H concentration ratio is preferably set to 10 or larger (the heavy hydrogen termination fraction D/(D+H) is higher than 90.9%) to significantly improve the characteristics of a semiconductor element. A High-k insulator as the insulator 5b is preferably AlO, which has a dielectric constant equal to or larger than eight, or may be ZrO₂, Ta₂O₅, TiO₂, HfO₂, HfSiO₄, La₂O₃, Y₂O₃, or ZrO₂. The characteristics of a semiconductor element can be improved by using such a high dielectric insulator having a dielectric constant equal to or larger than eight, with which the D/H concentration ratio is equal to or larger than 10.

As described above, when the D/H concentration ratio in the part of the insulator 5b, which is along the insulator 5a, and the insulator 5a is set to 10 or larger, the average D/H concentration ratio in a cell functional insulator including the part of the insulator 5b along 5a, the insulator 5a, the electric charge accumulation film 4, and the tunnel insulator 3 can be set to 10 or larger. The average fraction (D/(D+H)) of heavy hydrogen (D) termination in the cell functional insulator can exceed 90.9%. In this manner, the characteristics of the semiconductor storage element can be improved by increasing the overall average D/H concentration ratio and the heavy hydrogen (D) termination fraction in the cell functional insulator.

Comparative examples illustrated in FIGS. 8 and 9 include a plurality of exemplary manufacturing methods.

A first comparative example (E1) is an example in which the insulator 5b is formed (refer to FIG. 5), an RTP with nitrogen (N₂) annealing is performed, radical oxidation is performed, and annealing using heavy hydrogen (D₂) gas is performed. The RTP with nitrogen (N₂) annealing is performed under conditions of, for example, 1035° C. and 10 seconds. The RTP with nitrogen (N₂) annealing is performed for, for example, crystallization of the insulator 5b. The annealing using heavy hydrogen (D₂) gas is performed under conditions of, for example, 800° C. and 60 minutes. The annealing using heavy hydrogen (D₂) gas is performed for, for example, introduction of heavy hydrogen (D).

In a second comparative example (E2), reactivation annealing is performed after the annealing using heavy hydrogen (D₂) gas in the first comparative example. The reactivation annealing is, for example, spike annealing at 1015° C. The annealing using heavy hydrogen (D₂) gas is performed in a temperature zone in which dopant is inactivated. The reactivation annealing is performed for, for example, reactivation of dopant inactivated by the annealing using heavy hydrogen (D₂) gas.

As illustrated in FIG. 8, according to the first embodiment, the concentration of heavy hydrogen (D) in the insulators 5a and 5b can be improved as compared to the first and second comparative examples. As illustrated in FIG. 9, according to the first embodiment, the D/H concentration ratio in the insulators 5a and 5b can be improved as compared to the first and second comparative examples.

In the first and second comparative examples, radical oxidation is performed after crystallization of the insulator 5b. Trap levels T are potentially unlikely to be formed in the insulator 5b when the insulator 5b is crystallized. In the first and second comparative examples, introduction of heavy hydrogen (D) is performed after crystallization of the insulator 5b. The insulator 5b before crystallization is in an amorphous state containing a large number of dangling bonds. In the insulator 5b after crystallization, the number of dangling bonds largely decreases and the number of dangling bonds to be terminated with heavy hydrogen (D) is small, and thus it is potentially difficult to terminate dangling bonds with heavy hydrogen (D).

In the first and second comparative examples, heavy water (D₂O) is not used for introduction of heavy hydrogen (D).

Furthermore, in the first and second comparative examples, the reactivation annealing is performed.

However, in the first embodiment, crystallization of the insulator 5b is performed after radical oxidation. Accordingly, it is thought that a larger number of trap levels T are formed in the insulator 5a before crystallization and a large number of trap levels T remain after crystallization of the insulator 5b. Moreover, in the first embodiment, crystallization of the insulator 5b and introduction of heavy hydrogen (D) are substantially simultaneously performed. Accordingly, introduction of heavy hydrogen (D) is performed while dangling bonds remain in the insulator 5b. As a result, the dangling bonds are likely to be terminated with heavy hydrogen (D).

In the first embodiment, heavy water (D₂O) is used for introduction of heavy hydrogen (D). Heavy water (D₂O) is more likely to be separated into radicals and terminate dangling bonds with heavy hydrogen (D) atoms than heavy hydrogen (D₂), which is relatively stable. Moreover, heavy water (D₂O) is oxidizing species. Since O-D coupling is stable, light hydrogen (H) can be more efficiently replaced with heavy hydrogen (D) by producing Si—O-D coupling through an oxidation process rather than replacing Si—H coupling with Si-D coupling. Thus, the concentration of heavy hydrogen (D) can be made more likely to be improved by using heavy water (D₂O). As for a High-k insulator such as AlO, as well, light hydrogen in the insulators 5a and 5b can be made likely to be replaced with heavy hydrogen by replacing O—H coupling with O-D coupling. O—H coupling introduced by radicals through introduction of OH* into a High-k insulator by radical oxidation before heavy water (D₂O) treatment can be further replaced with O-D coupling. In this manner, a high dielectric insulator having the D/H concentration ratio of 10 or higher can be obtained.

In the first embodiment, introduction of heavy hydrogen (D) is performed by an RTP substantially simultaneously with crystallization of the insulator 5b. Accordingly, annealing using heavy hydrogen (D₂) gas is unnecessary. Thus, dopant is not inactivated and reactivation annealing is unnecessary.

A third comparative example (E3) is an example in which radical oxidation is performed after an RTP using heavy hydrogen (D₂) gas and heavy water (D₂O), in other words, the process illustrated in FIG. 6 is performed after the process illustrated in FIG. 7.

As illustrated in FIG. 8, in the first embodiment, the concentration of heavy hydrogen (D) in the insulators 5a and 5b can be improved as compared to the third comparative example. As illustrated in FIG. 9, in the first embodiment, the D/H concentration ratio in the insulators 5a and 5b can be improved as compared to the third comparative example.

In the third comparative example, as in the first and second comparative examples, radical oxidation is performed after crystallization of the insulator 5b.

However, in the first embodiment, crystallization of the insulator 5b is performed after radical oxidation. Accordingly, it is thought that a larger number of trap levels T are formed in the insulator 5a before crystallization and a large number of trap levels T remain after crystallization of the insulator 5b.

n the method described in the first embodiment, crystallization of the insulator 5b is performed after radical oxidation, but since the crystallization and replacement of light hydrogen with heavy hydrogen in the radical oxidation are mutually affecting processes, a significant amount of work is needed to improve device reliability degradation by combining process parameters (such as temperature, time, pressure, oxidation amount, temperature increase/decrease speed, and the order of crystallization, radical oxidation, and other annealing). However, degradation of device performance reliability can be reduced by considering the D/H concentration ratio in the insulators 5a and 5b and selecting a process that provides the part of the insulator 5b, which is along the insulator 5a and in which the D/H concentration ratio exceeds 10.

According to the above description, it is possible to form a structure in which the interfaces between the insulator 5a, the insulator 5b, the electric charge accumulation film 4, and the tunnel insulator 3 are terminated with heavy hydrogen (D) as in the present embodiment. Through repetition of write/erase operation, defects are generated in the electric charge accumulation film 4 and the tunnel insulator 3, and part of electric charge accumulated in the electric charge accumulation film 4 leaks through the defects. This can cause a data loss. Defects in the electric charge accumulation film 4 and the tunnel insulator 3 are thought to be generated as light hydrogen (H) intentionally or unintentionally introduced at memory cell formation is eliminated by electric stress through write/erase operation. Moreover, according to the present embodiment, the amount of a light hydrogen (H) component in the insulator 5a, which is eliminated by electric stress through write/erase operation can be reduced by increasing the D/H concentration ratio in the insulator 5a to 10 or larger. As a result, it is possible to reduce leakage of part of electric charge to the electrode layer 6, thereby improving the element characteristics.

When heavy hydrogen (D) is introduced into a SiN or SiON film, N—H coupling in the film is replaced with N-D coupling. N-D coupling has extremely stronger electric stress resistance than N—H coupling. In other words, robust coupling against electric stress can be obtained by replacing a place that would be a coupling defect with heavy hydrogen (D). Thus, it is possible to reduce degradation of the electric charge accumulation film 4 and the tunnel insulator 3 through write/erase operation by decreasing the number of N—H coupling sites and increasing the number of N-D coupling sites in the electric charge accumulation film 4 and the tunnel insulator 3. It is also possible to reduce false writing at writing and reading. In addition, it is possible to obtain an effect of reducing reliability degradation when write/erase operation is repeated. Thus, it is possible to obtain a semiconductor storage element that can reduce degradation of the reliability of a memory cell.

In the present embodiment, the structure with heavy hydrogen (D) termination can be also formed at the interface between the electric charge accumulation film 4 and the insulator 5a and the interface between the insulator 5a and the insulator 5b. Electric charge accumulated in the electric charge accumulation film 4 potentially leaks to the insulator 5a side. It is possible to further reduce leakage of electric charge in the electric charge accumulation film 4 by actively introducing heavy hydrogen (D) into the insulator 5a and the insulator 5b. Accordingly, the data holding characteristic and the cycle resistance can be improved, and the reliability of the memory cell can be improved.

In the present embodiment, treatment is performed to increase the concentration of heavy hydrogen (D) in the insulators 5a and 5b and decrease the concentration of light hydrogen (H). Accordingly, the data holding characteristic and the cycle resistance can be improved, and the reliability of the memory cell can be improved. In the first, second, and third comparative examples, the heavy hydrogen concentration in the electric charge accumulation film 4 and the tunnel insulator 3 was equivalent to that in an example, but in the first embodiment, the reliability of the memory cell was significantly improved. Although improvement of a memory cell reliability indicator with respect to memory cell reliability in the first comparative example was 40 in the second comparative example and 280 in the third comparative example, the memory cell reliability indicator in the first embodiment was improved by 1080.

In a modification of the present embodiment, a process using heavy hydrogen (D₂) gas and heavy water (D₂O) may be used as reactivation annealing. The D/H concentration ratio in the insulators 5a and 5b can be increased by performing, for example, spike annealing treatment at a treatment temperature equal to or higher than 1000° C. for a shorter holding time (for example, within five seconds) in heavy hydrogen (D₂) gas and heavy water (D₂O) atmosphere. The spike annealing treatment is annealing treatment with high temperature increase/decrease speed and a shortened stay time at a peak temperature in an RTP. Since heavy hydrogen (D) termination potentially reduces through subsequent process treatment, the D/H concentration ratio can be maintained high by performing a process using heavy hydrogen (D₂) gas and heavy water (D₂O) at the end of a manufacturing process with a high thermal load. For example, a process temperature using heavy hydrogen (D₂) gas and heavy water (D₂O) is higher than in all subsequent temperature processes in a manufacturing process. Through such a process, it is possible to obtain a device with an increased D/H concentration ratio and further reduction of reliability degradation. The memory cell reliability indicator in the present modification was improved by 1240.

After such an RTP using heavy hydrogen (D₂) gas and heavy water (D₂O) is performed, the barrier metal layer 6a and the electrode material layer 6b are sequentially formed on the surface of the insulator 5b in the hollow spaces H2 through a normal process (FIG. 10). As a result, the electrode layer 6 including the barrier metal layer 6a and the electrode material layer 6b is formed in each hollow space H2, and a multilayer film S2 alternately including the plurality of electrode layers 6 and the plurality of insulating layers 14 is formed on the insulator 12. Treatment that removes the sacrifice layers 13 and forms the insulator 5b, the barrier metal layer 6a, and the electrode material layer 6b is referred to as replacement treatment.

In this manner, the semiconductor storage element of the present embodiment is manufactured (FIG. 10). FIG. 1 illustrates part of the semiconductor storage element illustrated in FIG. 10.

As described above, according to the present embodiment, it is possible to obtain a semiconductor storage element that can reduce degradation of the reliability of the memory cell.

Second Embodiment

A semiconductor storage element of a second embodiment will be described below with reference to FIGS. 11 to 20. FIGS. 11 to 20 are cross-sectional views illustrating a method of manufacturing the semiconductor storage element of the second embodiment.

FIG. 11 illustrates a section after a slit (H5) is formed in the multilayer film S1 in the process illustrated in FIG. 4 and before the sacrifice layers 13 are removed through the process in FIG. 4. FIG. 11 illustrates the insulator 5a, the electric charge accumulation film 4, the tunnel insulator 3, the channel semiconductor layer 2, and the core insulator 1, which are sequentially formed in the memory hole H1. The insulator 5a, the electric charge accumulation film 4, and the tunnel insulator 3 in FIG. 11 are not removed from the bottom part of the memory hole H1 but remain. Such a structure is employed, for example, in a case where the multilayer film S1 is thick.

FIG. 11 additionally illustrates an insulator 21, a metal layer 22a, a lower semiconductor layer 22b, an insulator 23, a semiconductor layer 24, an insulator 25, an upper semiconductor layer 22c, an insulator 26, and a gate layer 27, which are sequentially formed above the substrate 11. The insulator 12 of the present embodiment is formed above the substrate 11 with these insulators and layers interposed therebetween in the process in FIG. 2. The insulator 21 is, for example, a silicon oxide film. The metal layer 22a is, for example, a W layer. The lower semiconductor layer 22b is, for example, a polysilicon layer. The insulator 23 is, for example, a silicon oxide film. The semiconductor layer 24 is, for example, a polysilicon layer. The insulator 25 is, for example, a silicon oxide film. The upper semiconductor layer 22c is, for example, a polysilicon layer. The insulator 26 is, for example, a silicon oxide film. The gate layer 27 is, for example, a polysilicon layer. The metal layer 22a, the lower semiconductor layer 22b, and the upper semiconductor layer 22c constitute a source line 22. Accordingly, the channel semiconductor layer 2 is electrically connected to the source line 22. Electrical connection between A and B may be direct connection between A and B or may be indirect connection between A and B through an electric conductor.

The memory hole H1 of the present embodiment is formed to reach the lower semiconductor layer 22b through the multilayer film S1, the insulator 12, the gate layer 27, the insulator 26, the upper semiconductor layer 22c, the insulator 25, the semiconductor layer 24, and the insulator 23 in the process in FIG. 2. The insulator 5a, the electric charge accumulation film 4, the tunnel insulator 3, the channel semiconductor layer 2, and the core insulator 1 are sequentially formed in the memory hole H1 in the process in FIG. 3.

In the process illustrated in FIG. 11, a slit H5 is formed to reach the semiconductor layer 24 through the multilayer film S1, the insulator 12, the gate layer 27, the insulator 26, the upper semiconductor layer 22c, and the insulator 25. The slit H5 is an example of a first recessed part. In the process in FIG. 11, an insulator 28 is also formed on the side and bottom surfaces of the slit H5. The insulator 28 is, for example, a SiN film.

Subsequently, the insulator 28 is removed from a bottom part of the slit H5 by etching, and the semiconductor layer 24 is removed by wet etching using the slit H5 (FIG. 12). As a result, a hollow space H6 is formed between the insulator 25 and the insulator 23. Subsequently, the insulator 25 and the insulator 23 are removed by chemical dry etching (CDE) using the slit H5 and the hollow space H6, and the insulator 5a, the electric charge accumulation film 4, and the tunnel insulator 3, which are exposed in the hollow space H6 are fabricated (FIG. 10). As a result, the volume of the hollow space H6 increases and the side surface of the channel semiconductor layer 2 is exposed in the hollow space H6.

Subsequently, a middle semiconductor layer 22d is formed in the hollow space H6 (FIG. 13). As a result, the middle semiconductor layer 22d is formed between the lower semiconductor layer 22b and the upper semiconductor layer 22c, and the source line 22 sequentially including the metal layer 22a, the lower semiconductor layer 22b, the middle semiconductor layer 22d, and the upper semiconductor layer 22c is formed. The middle semiconductor layer 22d is, for example, a polysilicon layer doped with phosphorus (P). The source line 22 is electrically connected to the channel semiconductor layer 2 through the middle semiconductor layer 22d.

Subsequently, the insulator 28 is removed from the slit H5 (FIG. 14). As a result, the side surface of the multilayer film S1 is exposed in the slit H5.

Subsequently, steam (H₂O) is supplied into the slit H5 to perform oxidation treatment (FIG. 15). As a result, the surfaces of the upper semiconductor layer 22c, the middle semiconductor layer 22d, and the gate layer 27 exposed in the slit H5 are oxidized by the steam, and accordingly, as illustrated in FIG. 16, an oxide film 22e (for example, a SiO film) is formed through the oxidation of the surface of the upper semiconductor layer 22c, an oxide film 22f (for example, a SiO film) is formed through the oxidation of the surface of the middle semiconductor layer 22d, and an oxide film 27a (for example, a SiO film) is formed through the oxidation of the surface of the gate layer 27.

Subsequently, the sacrifice layers 13 is removed with liquid chemical such as phosphoric acid by using the slit H5. As a result, a plurality of hollow spaces H2 are formed between the insulating layers 14 (FIG. 17). The upper semiconductor layer 22c, the middle semiconductor layer 22d, and the gate layer 27 are covered by the oxide films 22e, 22f, and 27a and thus not removed through the process in FIG. 17.

Subsequently, the insulator 5b containing AlO is formed on the surfaces of the insulating layers 14 and the insulator 5a in the hollow spaces H2 (FIG. 18). Thereafter, the thermal treatment described above in the first embodiment is performed to introduce heavy hydrogen (D) into the insulator 5b containing AlO, the insulator 5a containing SiO, the electric charge accumulation film 4 containing SiN, and the tunnel insulator 3 containing SiON (FIG. 19).

Subsequently, the barrier metal layer 6a and the electrode material layer 6b are sequentially formed on the surface of the insulator 5b in the hollow spaces H2 (FIG. 20). As a result, the block insulator 5 including the insulator 5a and the insulator 5b is formed. In addition, the electrode layer 6 including the barrier metal layer 6a and the electrode material layer 6b is formed in each hollow space H2, and the multilayer film S2 alternately including the plurality of electrode layers 6 and the plurality of insulating layers 14 is formed on the insulator 12. Subsequently, an insulator 29 is formed in the slit H5 (FIG. 20). The insulator 29 is, for example, a silicon oxide film.

In this manner, the semiconductor storage element of the second embodiment is manufactured (FIG. 20). FIG. 1 illustrates part of the semiconductor storage element illustrated in FIG. 20. The semiconductor storage element of the second embodiment can reduce degradation of the reliability of the memory cell as in the first embodiment.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims

1. A semiconductor storage element comprising: a laminated body in which insulating layers and conductive layers are alternately laminated in a first direction;a semiconductor layer disposed in the first direction in the laminated body;a first insulator disposed in the first direction between the laminated body and the semiconductor layer;a second insulator disposed in the first direction between the laminated body and the first insulator;a third insulator disposed in the first direction between the laminated body and the second insulator; anda fourth insulator including a first part and a second part, the first part being disposed between each of the conductive layers and the third insulator, the second part being disposed in a second direction intersecting the first direction between each of the conductive layers and the insulating layer and connected to the first part, whereinthe average concentration of heavy hydrogen in the first part is higher than the average concentration of heavy hydrogen in the third insulator, andthe ratio of heavy hydrogen concentration to light hydrogen concentration in the first part is smaller than the ratio of heavy hydrogen concentration to light hydrogen concentration in the third insulator.

2. The semiconductor storage element according to claim 1, wherein the ratio of heavy hydrogen concentration to light hydrogen concentration in at least one of the first part and the third insulator is equal to or larger than one.

3. The semiconductor storage element according to claim 2, wherein the ratio of heavy hydrogen concentration to light hydrogen concentration in at least one of the first part and the third insulator is equal to or larger than 10.

4. The semiconductor storage element according to claim 1, further comprising a first line disposed in the second direction, wherein the semiconductor layer is electrically connected to the first line.

5. The semiconductor storage element according to claim 1, wherein the first insulator contains silicon oxynitride,the second insulator contains silicon nitride,the third insulator contains silicon oxide, andthe fourth insulator contains aluminum oxide.

6. A semiconductor storage element comprising: a laminated body in which insulating layers and conductive layers are alternately laminated in a first direction;a semiconductor layer disposed in the first direction in the laminated body;a first insulator disposed in the first direction between the laminated body and the semiconductor layer;a second insulator disposed in the first direction between the laminated body and the first insulator;a third insulator disposed in the first direction between the laminated body and the second insulator; anda fourth insulator including a first part and a second part, the first part being disposed between each of the conductive layers and the third insulator, the second part being disposed in a second direction intersecting the first direction between each of the conductive layers and the insulating layer and connected to the first part, whereinthe first part includes a High-k film, andthe ratio of heavy hydrogen concentration to light hydrogen concentration in the High-k film is equal to or larger than 10.

7. A semiconductor storage element manufacturing method comprising: sequentially forming a first insulator, a second insulator, a third insulator, and a semiconductor layer, which extend in a first direction, in a second direction intersecting the first direction in a laminated body in which sacrifice layers and insulating layers are alternately laminated in the first direction;removing the sacrifice layer and forming a fourth insulator on a surface of a region from which the insulating layer is removed; andperforming spike annealing treatment for a holding time of five seconds or shorter at a treatment temperature of 1000° C. or higher by using heavy hydrogen (D2) gas and heavy water (D2O) to introduce heavy hydrogen (D) into the first insulator, the second insulator, the third insulator, and the fourth insulator.

8. The semiconductor storage element manufacturing method according to claim 7, wherein the treatment temperature of the spike annealing treatment is higher than a treatment temperature in a manufacturing process later than the spike annealing treatment.

9. The semiconductor storage element manufacturing method according to claim 7, wherein carrier gas of heavy water (D2O) in the spike annealing treatment contains argon (Ar) or nitrogen (N2).