This application claims the priority of Chinese Patent Application No. 202210514708.3, submitted to the Chinese Intellectual Property Office on May 12, 2022, the disclosure of which is incorporated herein in its entirety by reference.
The present disclosure relates to the field of semiconductor integrated circuit manufacturing technologies, in particular to a semiconductor structure and a manufacturing method thereof.
As a semiconductor memory commonly used in an electronic device such as a computer, a dynamic random access memory (DRAM) includes a plurality of memory cells. The memory cell includes a memory capacitor, and a transistor electrically connected to the memory capacitor. The transistor includes a gate, a source region, and a drain region. The gate of the transistor is electrically connected to a word line. The source region of the transistor is used to form a bit line contact region to be electrically connected to a bit line by using a bit line contact structure. The drain region of the transistor is used to form a memory node contact region to be electrically connected to the memory capacitor by using a memory node contact structure.
With the continuous development of semiconductor technologies, critical dimensions of devices in an integrated circuit continue to shrink. After the semiconductor process has entered the phase of deep submicron, the size of the DRAM becomes smaller.
Accordingly, transistors have gradually evolved from a buried gate structure to a gate-all-around (GAA) structure that occupies a smaller area. The structure of the memory capacitor has also been adjusted from hexagonal closest packing to quadrilateral packing. Moreover, the radial dimension of the memory capacitor is still shrinking. For example, the memory capacitor is further adjusted from a cup-shaped structure to a columnar structure.
However, the radial dimension of the memory capacitor is decreasing continuously, while a higher depth-to-width ratio tends to increase the etching difficulty and limit the height of the memory capacitor. This also reduces the surface area of the memory capacitor significantly, resulting in a smaller capacity of the memory capacitor, which fails to meet the usage requirements.
Accordingly, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof.
To achieve the foregoing objective, according to an aspect, some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes: a base and a capacitor structure. The base is provided with a capacitive contact structure. The capacitor structure is connected to the capacitive contact structure. The capacitor structure includes a plurality of capacitor units stacked in a direction vertical to the capacitive contact structure.
According to another aspect, some embodiments of the present disclosure provide a method of manufacturing a semiconductor structure, including the following steps:
To describe the technical solutions in the embodiments of the present disclosure or in the prior art more clearly, the following briefly describes the drawings required for describing the embodiments or the prior art. Apparently, the drawings in the following description merely show some embodiments of the present disclosure, and a person of ordinary skill in the art may still derive other drawings from these drawings without creative efforts.
To facilitate the understanding of the present disclosure, the present disclosure is described more completely below with reference to the related accompanying drawings. The preferred embodiments of the present disclosure are shown in the accompanying drawings. However, the present disclosure may be embodied in various forms without being limited to the embodiments described herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and comprehensive.
Unless otherwise defined, all technical and scientific terms used in the specification have the same meaning as commonly understood by those skilled in the technical field of the present disclosure. The terms used in the specification of the present disclosure are merely for the purpose of describing specific embodiments, rather than to limit the present disclosure.
It should be understood that when an element or a layer is described as “being on”, “being adjacent to”, “being connected to” or “being coupled to” another element or layer, it can be on, adjacent to, connected to, or coupled to the another element or layer directly, or intervening elements or layers may be present. On the contrary, when an element is described as “being directly on”, “being directly adjacent to”, “being directly connected to” or “being directly coupled to” another element or layer, there are no intervening elements or layers.
Spatial relationship terms such as “under”, “beneath”, “lower”, “below”, “above”, and “upper” can be used herein to describe the relationship shown in the figure between one element or feature and another element or feature. It should be understood that in addition to the orientations shown in the figure, the spatial relationship terms further include different orientations of used and operated devices. For example, if a device in the accompanying drawings is turned over, an element or feature described as being “beneath another element”, “below it”, or “under it” is oriented as being “on” the another element or feature. Therefore, the exemplary terms “beneath” and “under” may include two orientations of above and below. In addition, the device may further include other orientations (for example, a rotation by 90 degrees or other orientations), and the spatial description used herein is interpreted accordingly.
In the specification, the singular forms of “a”, “an” and “the/this” may also include plural forms, unless clearly indicated otherwise. It should also be understood that the terms such as “including/comprising” and “having” indicate the existence of the stated features, wholes, steps, operations, components, parts or combinations thereof. However, these terms do not exclude the possibility of the existence of one or more other features, wholes, steps, operations, components, parts or combinations thereof. In this case, in this specification, the term “and/or” includes any and all combinations of related listed items.
Embodiments of the present disclosure are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments (and intermediate structures) of the present disclosure, such that variations shown in the shapes and due to, for example, manufacturing techniques and/or tolerances can be contemplated. Therefore, the embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. The regions shown in the figure are schematic in nature, and their shapes are not intended to show actual shapes of the regions of the device or limit the scope of the present disclosure.
With the continuous development of semiconductor technologies, critical dimensions of devices in an integrated circuit continue to shrink. After the semiconductor process has entered the phase of deep submicron, the size of the DRAM becomes smaller. Accordingly, transistors have gradually evolved from a buried gate structure to a gate-all-around (GAA) structure that occupies a smaller area. The structure of the memory capacitor has also been adjusted from hexagonal closest packing to quadrilateral packing. Moreover, the radial dimension of the memory capacitor is still shrinking. For example, the memory capacitor is further adjusted from a cup-shaped structure to a columnar structure.
However, the radial dimension of the memory capacitor is decreasing continuously, while a higher depth-to-width ratio tends to increase the etching difficulty and limit the height of the memory capacitor. This also reduces the surface area of the memory capacitor significantly, resulting in a smaller capacity of the memory capacitor, which fails to meet the usage requirements.
In some embodiments, the insufficient capacity can be compensated by increasing the K value of the dielectric layer in the memory capacitor. However, a dielectric material with a higher K value tends to have a narrower band gap is prone to more severe leakage, making it difficult to find a suitable capacitor dielectric material.
Accordingly, some embodiments of the present disclosure provide a semiconductor structure. By means of epitaxial growth and self-alignment, capacitor units are stacked in a direction vertical to a capacitive contact structure, to obtain a relatively high capacitor structure. It is ensured that the formed capacitor structure is structurally stable and has a high capacity, thereby effectively improving the electrical performance and production yield of the semiconductor structure.
Referring to
In some embodiments, the base 1 may be made of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The base 1 may be of a single-layer structure or a multi-layer structure. For example, the base 1 may be a silicon (Si) base, a silicon germanium (SiGe) base, a silicon germanium carbon (SiGeC) base, a silicon carbide (SiC) base, a gallium arsenide (GaAs) base, an indium arsenide (InAs) base, an indium phosphide (InP) base, or another III/V semiconductor base or II/VI semiconductor base. Alternatively, in another example, the base 1 may be a layered base including, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.
Optionally, the base 1 is a silicon base or a silicon-based base. As shown in
The gate-all-around transistor is a vertical gate-all-around transistor, which can have a high degree of integration in a vertical direction, thereby effectively reducing a planar area occupied by the transistor, so as to increase an integration density of the transistors. Moreover, it is easier to vertically stack multiple layers of capacitor units above, to effectively improve the memory integration density of the semiconductor structure.
In the embodiments of the present disclosure, a capacitor structure C0 is connected to the capacitive contact structure SNC, and the capacitor structure C0 includes a plurality of capacitor units 2 stacked in a direction vertical to the capacitive contact structure SNC. That is, the plurality of capacitor units may be stacked in a self-aligned manner based on the capacitive contact structure SNC. Moreover, a stacking manner of the plurality of capacitor units 2 may be selected as needed.
In some embodiments, referring to
For example, the capacitive connection structure 20 is located vertically above the capacitive contact structure SNC, and in any adjacent two of the capacitor units 2 in a direction perpendicular to the capacitive contact structure SNC (e.g., direction Z), the capacitive connection structures 20 are interconnected and connected to the capacitive contact structure SNC. That is, the capacitive connection structure 20 in the bottom capacitor unit CD may be directly connected to the capacitive contact structure SNC, while the capacitive connection structures 20 in the capacitor units 2 stacked in other layers may be sequentially connected in series through the capacitive connection structure 20 below, so as to be connected to the capacitive contact structure SNC.
Optionally, the capacitive connection structure 20 may be formed through an epitaxial growth process. The capacitive connection structure 20 may be a conductive structure made of silicon germanium (SiGe) or other conductive materials capable of unidirectional growth along a (100) crystalline surface. The capacitive connection structure 20 is located vertically above the capacitive contact structure SNC, and may be formed in a self-aligned manner based on the capacitive contact structure SNC. That is, orthographic projection of the capacitive connection structure 20 on the base 1 may coincide with orthographic projection of the capacitive contact structure SNC on the base 1. The capacitive connection structure 20 is, for example, a conductive pillar, and the orthographic projection of the capacitive connection structure 20 on the base 1 may be circular, elliptical, or polygonal, which is not limited in the embodiments of the present disclosure.
For example, the first electrode 21 may be located on a sidewall of the capacitive connection structure 20, and in any adjacent two of the capacitor units 2 in the direction vertical to the capacitive contact structure SNC (e.g., direction Z), the first electrodes 21 are interconnected. The high-K dielectric layer 22 is arranged on a sidewall of the first electrode 21, and in any adjacent two of the capacitor units 2 in the direction vertical to the capacitive contact structure SNC (e.g., direction Z), the high-K dielectric layers 22 are interconnected. The second electrode 23 is arranged on a sidewall of the high-K dielectric layer 22, and in any adjacent two of the capacitor units 2 in the direction vertical to the capacitive contact structure SNC, the second electrodes 23 are interconnected.
In some embodiments, further referring to
Herein, the top dielectric layer 4 is made of an insulating material, for example, at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The top dielectric layer 4 has the opening K, and the second electrode 23 in the top capacitor unit CT may be exposed from the opening K. The common-source electrode layer 5 covers the top dielectric layer 4, and is connected to the second electrode 23 through the opening K, such that the second electrodes 23 in a plurality of capacitor units 2 in a direction parallel to the base 1 (e.g., direction X) are interconnected and an electrical signal is provided to each second electrode 23. The common-source electrode layer 5 may be made of a metal or metal compound with good conductivity, for example, silicon germanium (SiGe).
It should be noted that, further referring to
Further referring to
Optionally, an upper surface of the support structure 3 away from the base 1 is flush with a top surface of the second electrode 23 away from the base 1. That is, the support structure 3 can fill up the groove G, to ensure that adjacent capacitor units 2 in the same layer can be effectively supported by the support structure 3 and form a flat surface, to facilitate stacking of more capacitor units 2.
It is understandable that, the shape and material of the support structure 3 may be designed based on the stacking position of the capacitor unit 2 and the structure of the groove G.
For example, in the top capacitor unit CT shown in
For example, in the bottom capacitor unit CD and the intermediate capacitor unit CM shown in
In addition, in the bottom capacitor unit CD and the intermediate capacitor unit CM shown in
In other embodiments, referring to
For example, as shown in
Optionally, the first electrode 21 may be formed through an epitaxial growth process. The first electrode 21 may be a conductive structure made of silicon germanium (SiGe) or other conductive materials capable of unidirectional growth along a (100) crystalline surface. The first electrode 21 is located vertically above the capacitive contact structure SNC, and may be formed in a self-aligned manner based on the capacitive contact structure SNC. That is, orthographic projection of the first electrode 21 on the base 1 may coincide with orthographic projection of the capacitive contact structure SNC on the base 1. The first electrode 21 is, for example, a conductive pillar, and the orthographic projection of the first electrode 21 on the base 1 may be circular, elliptical, or polygonal, which is not limited in the embodiments of the present disclosure.
For example, the high-K dielectric layer 22 is arranged on a sidewall of the first electrode 21, and in any adjacent two of the capacitor units 2 in the direction vertical to the capacitive contact structure SNC (e.g., direction Z), the high-K dielectric layers 22 are interconnected. The second electrode 23 is arranged on a sidewall of the high-K dielectric layer 22, and in any adjacent two of the capacitor units 2 in the direction vertical to the capacitive contact structure SNC (e.g., direction Z), the second electrodes 23 are interconnected.
In some embodiments, further referring to
In addition, the second electrode 23 may be made of a metal or metal compound with good conductivity, for example, made of titanium nitride (TiN) through atomic layer deposition. The high-K dielectric layer 22 may be selected according to an actual requirement, and may be, for example, a silicon nitride layer. This is not limited in the embodiments of the present disclosure.
In some embodiments, further referring to
It should be noted that, further referring to
Further referring to
Optionally, an upper surface of the support structure 3 away from the base 1 is flush with a top surface of the second electrode 23 away from the base 1. That is, the support structure 3 can fill up the groove G, to ensure that adjacent capacitor units 2 in the same layer can be effectively supported by the support structure 3 and form a flat surface, to facilitate stacking of more capacitor units 2.
It is understandable that, the shape and material of the support structure 3 may be designed based on the stacking position of the capacitor unit 2 and the structure of the groove G.
For example, in the top capacitor units CT shown in
For example, in the bottom capacitor unit CD and the intermediate capacitor unit CM shown in
In addition, in the bottom capacitor unit CD and the intermediate capacitor unit CM shown in
As described above, in the semiconductor structure provided by the embodiments of the present disclosure, a plurality of capacitor units 2 can be stacked in a direction perpendicular to a capacitive contact structure SNC (e.g., direction Z), to form a capacitor structure C0. In this way, while the radial size of the capacitor structure shrinks continuously, the depth-to-width ratio of the capacitor unit 2 in each layer can be reduced, and etching with a high depth-to-width ratio can be avoided, thereby eliminating the problem of increased etching difficulty caused by a higher depth-to-width ratio. Thus, the process difficulty of the capacitor structure C0 is greatly reduced, and the stability of the capacitor structure C0 is effectively improved, to avoid stack collapsing of the capacitor structure C0. Moreover, in the embodiments of the present disclosure, by means of epitaxial growth and self-alignment, the capacitor units 2 are stacked in the direction vertical to the capacitive contact structure SNC, which can further reduce the number of masks in use and effectively reduce stacking deviation, thereby further reducing the process difficulty of the capacitor structure.
In addition, in the embodiments of the present disclosure, by stacking a plurality of capacitor units 2, a relatively high capacitor structure C0 can be obtained, to ensure that the formed capacitor structure C0 has a relatively large capacitance area. In this way, it is ensured that the formed capacitor structure is structurally stable and has a high capacity while the size of the semiconductor structure is reduced repeatedly C0, thereby effectively improving the electrical performance and production yield of the semiconductor structure.
According to another aspect, some embodiments of the present disclosure provide a method of manufacturing a semiconductor structure, for manufacturing the semiconductor structure in the foregoing embodiments. The manufacturing method has all the technical advantages of the semiconductor structure described above. Details are not described herein again. Referring to
S100: Provide a base, where the base is provided with a capacitive contact structure.
S200: Stack a plurality of capacitor units in a direction vertical to the capacitive contact structure to form a capacitor structure. The capacitor structure is connected to the capacitive contact structure.
It can be understood that a method of manufacturing the capacitor unit varies with a structure of the capacitor unit. Manufacturing methods of the two semiconductor structures shown in
Referring to
S210: Form a bottom capacitor unit vertically above the capacitive contact structure.
For example, a capacitive connection structure is formed vertically above the capacitive contact structure, and a first electrode, a high-K dielectric layer, and a second electrode are sequentially formed on a sidewall of the capacitive connection structure.
S220: Stack an intermediate capacitor unit layer by layer vertically above the bottom capacitor unit.
For example, there may be one or more layers of intermediate capacitor units. If the bottom capacitor unit is considered as a first-layer capacitor unit, the intermediate capacitor unit may be in an (N+1)-th layer, where N is a positive integer and 2≤N+1≤M. Accordingly, forming the intermediate capacitor unit in an (N+1)-th layer includes: forming a capacitive connection structure of the (N+1)-th layer vertically above a capacitive connection structure of an N-th layer, and sequentially forming a first electrode, a high-K dielectric layer, and a second electrode on a sidewall of the capacitive connection structure of the (N+1)-th layer. That is, the intermediate capacitor units may be stacked from the second layer to an M-th layer.
In the embodiments of the present disclosure, the capacitive connection structures may epitaxially grown repeatedly; the capacitor units are stacked in a self-aligned manner, and the height of the capacitor structure is increased. The number of stacked layers is not limited, which can be selected as needed.
S230: Stack a top capacitor unit vertically above the intermediate capacitor unit.
For example, a capacitive connection structure of an (M+1)-th layer is formed vertically above a capacitive connection structure of an M-th layer, and a first electrode, a high-K dielectric layer, and a second electrode are sequentially formed on a sidewall of the capacitive connection structure of the (M+1)-th layer.
In some embodiments, further referring to
S300: Form a top dielectric material layer covering the top capacitor unit.
S400: Pattern the top dielectric material layer to form a top dielectric layer. The top dielectric layer has an opening, and the second electrode of the top capacitor unit is exposed from the opening.
S500: Form a common-source electrode layer covering the top dielectric layer, where the common-source electrode layer is connected to the second electrode.
To illustrate the foregoing manufacturing method more clearly, the following embodiments are described with reference to
In step S100, referring to
For the arrangement manner of the base 1 and the capacitive contact structures SNC herein, reference may be made to related description in the foregoing embodiments.
It is understandable that, after the capacitive contact structure SNC is formed on the base 1, the surface of the base 1 is generally polished. For example, chemical mechanical polishing is performed, such that the surface of the base 1 has better surface quality, to facilitate subsequent epitaxial growth of a capacitive connection structure 20 or a first electrode 21 on the base 1.
In step S210, referring to
S210A: Form a capacitive connection structure 20 vertically above the capacitive contact structure SNC, as shown in
For example, the capacitive connection structure 20 is formed through an epitaxial growth process. That is, the capacitive connection structure 20 may be epitaxially grown on the surface of the capacitive contact structure SNC, such that the capacitive connection structure 20 is self-aligned with the capacitive contact structure SNC.
S210B: Form a first electrode 21 on a sidewall of the capacitive connection structure 20, as shown in
S210C: Sequentially deposit a high-K dielectric material layer 220 and a second electrode material layer 230, as shown in
Optionally, in an example in which the semiconductor structure further includes the support structures 3, referring to
In some examples in which the support structure 3 further includes the support portion 32, referring to
Herein, it is understandable that the method of manufacturing the support structure 3 may be adjusted adaptively as the support structure 3 varies.
S210D: Remove part of the high-K dielectric material layer 220 and part of the second electrode material layer 230, to form a high-K dielectric layer 22 located on a sidewall of the first electrode 21 and a second electrode 23 located on a sidewall of the high-K dielectric layer 22, as shown in
In step S220, referring to
S220A: Form a first-layer capacitive connection structure 20 of the intermediate capacitor unit CM vertically above the capacitive connection structure 20 in the bottom capacitor unit CD, as shown in
For example, the capacitive connection structure 20 is formed through an epitaxial growth process. That is, an upper-layer capacitive connection structure 20 may be epitaxially grown on the surface of a lower-layer capacitive connection structure 20, to achieve self-alignment between the capacitive connection structures 20 in the two layers.
It is understandable that, after the capacitive connection structure 20 is formed, in the intermediate capacitor units CM at any layers, identical structures are manufactured by a same method. Therefore, manufacturing of other structures in the intermediate capacitor unit CM in one layer is used as an example for description.
S220B: Form a first electrode 21 on a sidewall of the capacitive connection structure 20, as shown in
S220C: Sequentially deposit a high-K dielectric material layer 220 and a second electrode material layer 230, as shown in
Optionally, in an example in which the semiconductor structure further includes the support structures 3, further referring to
In some examples in which the support structure 3 further includes the support portion 32, referring to
Herein, it is understandable that the method of manufacturing the support structure 3 may be adjusted adaptively as the support structure 3 varies.
S220D: Remove part of the high-K dielectric material layer 220 and part of the second electrode material layer 230, to form a high-K dielectric layer 22 located on a sidewall of the first electrode 21 and a second electrode 23 located on a sidewall of the high-K dielectric layer 22, as shown in
In step S230, referring to
S230A: Form a capacitive connection structure 20 of the top capacitor unit CT vertically above the top-layer capacitive connection structure 20 in the intermediate capacitor unit CM, as shown in
For example, the capacitive connection structure 20 is formed through an epitaxial growth process. That is, an upper-layer capacitive connection structure 20 may be epitaxially grown on the surface of a lower-layer capacitive connection structure 20, such that the capacitive connection structure 20 in the top capacitor unit CT is self-aligned with the capacitive connection structure 20 in the intermediate capacitor unit CM.
S230B: Form a first electrode 21 on a sidewall of the capacitive connection structure 20, as shown in
S230C: Sequentially deposit a high-K dielectric material layer 220 and a second electrode material layer 230, as shown in
Optionally, in an example in which the semiconductor structure further includes the support structures 3, further referring to
Herein, it is understandable that the method of manufacturing the support structure 3 may be adjusted adaptively as the support structure 3 varies.
S230D: Remove part of the high-K dielectric material layer 220 and part of the second electrode material layer 230, to form a high-K dielectric layer 22 located on a sidewall of the first electrode 21 and a second electrode 23 located on a sidewall of the high-K dielectric layer 22, as shown in
In step S300, referring to
In step S400, referring to
Optionally, further referring to
In step S500, referring to
Optionally, further referring to
Referring to
S210′: Form a bottom capacitor unit vertically above the capacitive contact structure.
For example, a first electrode is formed vertically above the capacitive contact structure, and a high-K dielectric layer and a second electrode are sequentially formed on a sidewall of the first electrode.
S220′: Stack one or more intermediate capacitor units layer by layer vertically above the bottom capacitor unit.
For example, there may be one or more layers of intermediate capacitor units. If the bottom capacitor unit is considered as a first-layer capacitor unit, the intermediate capacitor unit may be in an (N+1)-th layer, where N is a positive integer and 2≤N+1≤M. Accordingly, forming the intermediate capacitor unit in an (N+1)-th layer includes: forming a first electrode of the (N+1)-th layer vertically above a first electrode of an N-th layer, and sequentially forming a high-K dielectric layer and a second electrode on a sidewall of the first electrode of the (N+1)-th layer. That is, the intermediate capacitor units may be stacked from the second layer to an M-th layer.
S230′: Stack a top capacitor unit vertically above the intermediate capacitor unit.
For example, a first electrode of an (M+1)-th layer is formed vertically above a first electrode of an M-th layer, and a high-K dielectric layer and a second electrode are sequentially formed on a sidewall of the first electrode of the (M+1)-th layer.
Optionally, before the sequentially forming a high-K dielectric layer and a second electrode on a sidewall of the first electrode, the manufacturing method further includes: forming a barrier layer on the sidewall of the first electrode, and sequentially forming a high-K dielectric layer and a second electrode in a direction moving away from the first electrode.
In some embodiments, further referring to
S300′: Form a common-source electrode layer covering a sidewall of the second electrode in the top capacitor unit and a top surface of the second electrode away from the base.
To illustrate the foregoing manufacturing method more clearly, the following embodiments are described with reference to
In step S210′, referring to
S210′A: Form a first electrode 21 vertically above the capacitive contact structure SNC, as shown in
For example, the first electrode 21 is formed through an epitaxial growth process. That is, the first electrode 21 may be epitaxially grown on the surface of the capacitive contact structure SNC, such that the first electrode 21 is stacked on the capacitive contact structure SNC in a self-aligned manner.
S210′B: Sequentially deposit a high-K dielectric material layer 220 and a second electrode material layer 230 on a sidewall of the first electrode 21, as shown in
Optionally, in an example in which the semiconductor structure further includes the barrier layer 24, further referring to
Optionally, in an example in which the semiconductor structure further includes the support structures 3, further referring to
In some examples in which the support structure 3 further includes the support portion 32, further referring to
Herein, it is understandable that the method of manufacturing the support structure 3 may be adjusted adaptively as the support structure 3 varies.
S210′C: Remove part of the high-K dielectric material layer 220 and part of the second electrode material layer 230, to form a high-K dielectric layer 22 located on a sidewall of the first electrode 21 and a second electrode 23 located on a sidewall of the high-K dielectric layer 22, as shown in
Optionally, further referring to
Thus, preparation of the bottom capacitor unit CD is completed.
In step S220′, referring to
S220′A: Form a first-layer first electrode 21 of the intermediate capacitor unit CM vertically above the first electrode 21 in the bottom capacitor unit CD, as shown in
For example, the first electrode 21 is formed through an epitaxial growth process. That is, an upper-layer first electrode 21 may be epitaxially grown on the surface of a lower-layer first electrode 21, to achieve self-alignment between the first electrodes 21 in the two layers.
It is understandable that, after the first electrode 21 is formed, in the intermediate capacitor units CM at any layers, identical structures are manufactured by a same method. Therefore, manufacturing of other structures in the intermediate capacitor unit CM in one layer is used as an example for description.
S220′B: Sequentially deposit a high-K dielectric material layer 220 and a second electrode material layer 230 on a sidewall of the first electrode 21, as shown in
Optionally, in an example in which the semiconductor structure further includes the barrier layer 24, further referring to
Optionally, in an example in which the semiconductor structure further includes the support structures 3, further referring to
In some examples in which the support structure 3 further includes the support portion 32, further referring to
Herein, it is understandable that the method of manufacturing the support structure 3 may be adjusted adaptively as the support structure 3 varies.
S220′C: Remove part of the high-K dielectric material layer 220 and part of the second electrode material layer 230, to form a high-K dielectric layer 22 located on a sidewall of the first electrode 21 and a second electrode 23 located on a sidewall of the high-K dielectric layer 22, as shown in
Optionally, further referring to
Thus, preparation of the intermediate capacitor unit CM is completed.
In step S230, referring to
S230′A: Form a first electrode 21 of the top capacitor unit CT vertically above the top-layer first electrode 21 in the intermediate capacitor unit CM, as shown in
For example, the first electrode 21 is formed through an epitaxial growth process. That is, an upper-layer first electrode 21 may be epitaxially grown on the surface of a lower-layer first electrode 21, such that the first electrode 21 of the top capacitor unit CT is stacked on the first electrode 21 of the intermediate capacitor unit CM in a self-aligned manner.
S230′B: Sequentially deposit a high-K dielectric layer 22 and a second electrode layer 23 on a structure obtained after the first electrode 21 is formed, as shown in
Optionally, in an example in which the semiconductor structure further includes the barrier layer 24, further referring to
Thus, preparation of the top capacitor unit CT is completed.
Step S300′: Form a common-source electrode layer 5 covering a sidewall of the second electrode 23 in the top capacitor unit CT and a top surface of the second electrode 23 away from the base 1, as shown in
The common-source electrode layer 5 covers the second electrodes 23, such that the second electrodes 23 in a plurality of capacitor units 2 in a direction parallel to the base 1 are interconnected and an electrical signal is provided to each second electrode 23. The common-source electrode layer 5 may be made of a metal or metal compound with good conductivity through deposition, for example, made of silicon germanium (SiGe) through deposition. Moreover, the common-source electrode layer 5 covers the second electrodes 23, and can fill up the groove G between adjacent second electrodes 23 in the top capacitor units CT. That is, the support structure 3 in the groove G between adjacent second electrodes 23 in the top capacitor units CT may be omitted, such that a part filled with the common-source electrode layer 5 is used to achieve a supporting function.
The semiconductor manufacturing method provided in the embodiments of the present disclosure is used for manufacturing the semiconductor structure in the foregoing embodiments. The manufacturing method has all the technical advantages of the semiconductor structure described above. Details are not described herein again.
In addition, the deposition process mentioned in the embodiments of the present disclosure includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).
It should be understood that the execution order of some steps in the embodiments of the present disclosure is not strictly limited, and these steps may be executed simultaneously or in other orders. Moreover, in the embodiments of the present disclosure, at least some of the steps of the manufacturing method may include a plurality of sub-steps or stages. The sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of the sub-steps or stages is not necessarily carried out sequentially, but may be executed alternately with other steps or at least some of the sub-steps or stages of other steps.
The technical characteristics of the foregoing embodiments can be employed in arbitrary combinations. To provide a concise description of these examples, all possible combinations of all technical characteristics of the embodiment may not be described; however, these combinations of technical characteristics should be construed as disclosed in the description as long as no contradiction occurs.
The above embodiments are only intended to illustrate several implementations of the present disclosure in detail, and they should not be construed as a limitation to the patentable scope of the present disclosure. It should be noted that those of ordinary skill in the art can further make variations and improvements without departing from the conception of the present disclosure. These variations and improvements all fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope defined by the claims.
Number | Date | Country | Kind |
---|---|---|---|
202210514708.3 | May 2022 | CN | national |