A Dynamic Random Access Memory (DRAM) is a semiconductor memory capable of writing and reading data at a high speed and randomly, and is widely applied to a data storage device or apparatus. The DRAM is composed of a plurality of repeated storage units. Each storage unit generally includes a capacitor and a transistor. The capacitor stores data information. The transistor controls the reading of the data information in the capacitor. The capacitor is generally vertically arranged on a substrate. With the continuous improvement of the integration degree of a semiconductor structure, the capacitor has a large aspect ratio, which is not conducive to the manufacturing of the capacitor.
In order to improve the integration degree of the semiconductor structure, in the related art, the arrangement mode of the capacitor is converted from vertical arrangement into horizontal arrangement. However, the horizontally arranged capacitor causes the deformation of the semiconductor structure easily, thereby affecting the yield of the semiconductor structures.
The disclosure relates to the technical field of semiconductors, and in particular, to a semiconductor structure and a method for manufacturing the same.
A first aspect of the embodiments of the disclosure provides a method for manufacturing a semiconductor structure, which includes that: a substrate is provided. The substrate includes a first area and a second area connected to the first area.
A stack structure is formed on the substrate.
A plurality of columns of silicon pillar structures and support structures are formed in the stack structure located on the second area. The plurality of columns of silicon pillar structures are arranged at intervals in a first direction. Each column of silicon pillar structure includes a plurality of silicon pillars that are arranged at intervals and are parallel to the substrate. The plurality of silicon pillars in the plurality of columns of silicon pillar structures are distributed in a plurality of layers. The support structure is configured to connect any adjacent silicon pillar.
A capacitor structure surrounding each of the silicon pillars is formed.
In a second aspect of the embodiments of the disclosure, there is provided a semiconductor structure. The semiconductor structure is obtained by the method for manufacturing a semiconductor structure provided in the first aspect.
In order to more clearly illustrate the embodiments of the disclosure or the technical solutions in the related art, the drawings used in the description of the embodiments or the related art will be briefly described below. It is apparent that the drawings in the following description are some embodiments of the disclosure, and other drawings can be obtained by those skilled in the art according to these drawings without any creative work.
As described in the BACKGROUND, in a related art, there is a problem of deformation of silicon pillars during manufacturing a horizontal capacitor structure. The inventors have found that the main reason for this problem is that: when a plurality of silicon pillars distributed in an array are manufactured, there is no support structure between adjacent silicon pillars, which causes tilting or bending of silicon pillars under the action of their own weight, thereby reducing the yield of semiconductor structures.
Based on the abovementioned technical problem, in the semiconductor structure and the method for manufacturing the same provided by the embodiments of the disclosure, the support structures are also formed while silicon pillars in a plurality of layers and a plurality of columns are formed, and any adjacent silicon pillars are connected by using the support structure, so that the silicon pillar can be prevented from deforming due to its own weight, improving the strength of the plurality of columns of silicon pillars, thereby preventing the silicon pillar from tilting or bending during the manufacturing of a capacitor structure, and thus improving the yield of the semiconductor structures.
In order to make the abovementioned objectives, features, and advantages of the embodiments of the disclosure more apparent and easier to understand, the technical solutions in the embodiments of the disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the disclosure. It is apparent that the described embodiments are only part rather than all embodiments of the disclosure. Based on the embodiments in the disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the disclosure.
Referring to
At S100: a substrate is provided. The substrate includes a first area and a second area connected to the first area.
Referring to
The substrate 10 includes a first area and a second area connected to the first area. The first area is configured to form the semiconductor devices, such as a transistor, a word line, and a bit line. The second area is configured to form a capacitor structure.
It is to be noted that the first area is connected with the second area. It can be understood that the first area and the second area are arranged side by side. Reference is continued to be made to
At S200: a stack structure is formed on the substrate.
Exemplarily, referring to
The plurality of initial silicon layers 21 and the plurality of first initial sacrificial layers 22 are sequentially stacked and alternately arranged in a direction perpendicular to the substrate 10. The first initial sacrificial layers 22 are arranged on the substrate 10. The numbers of the initial silicon layers 21 and the first initial sacrificial layers 22 may be set according to actual requirements.
In some possible implementation modes, the initial silicon layers 21 and the first initial sacrificial layers 22 may be formed through a deposition process. The deposition process may include a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, or an Atomic Layer Deposition (ALD), etc.
In some another possible implementation modes, the first initial sacrificial layers 22 is formed by an Epitaxy (EPI) process. Thus, the problem of lattice mismatch between the first initial sacrificial layer 22 and the initial silicon layer 21 can be avoided. The material of the first initial sacrificial layer 22 includes SiGe, so that the first initial sacrificial layer 22 and the initial silicon layer 21 have a great etching selectivity ratio, so as to selectively remove the first sacrificial layer by a subsequent process, and reduce the etching of the silicon layer.
In addition, the first initial sacrificial layer 22 also provides certain support for the initial silicon layer 21 to ensure the normal progress of a process for manufacturing the semiconductor structure.
Referring to
The initial mask layer 50 may be a single film layer or a laminated structure. When the initial mask layer 50 is a laminated structure, the initial mask layer 50 may include a first initial mask layer 51 and a second initial mask layer 52. The first initial mask layer 51 is arranged on the stack structure 20, and the second initial mask layer 52 is arranged on the first initial mask layer 51. Thus, the mask pattern can be transferred into the second initial mask layer 52 first, then, the first initial mask layer 51 is etched with the second initial mask layer 52 with the mask pattern as a mask, so as to transfer the mask pattern onto the first initial mask layer 51, and finally, the stack structure 20 is etched with the first initial mask layer 51 with the mask pattern as the mask. Thus, the accuracy in a process of transferring the mask pattern can be improved, and thereby the manufacturing accuracy of the semiconductor structure can be improved.
The material of the first initial mask layer 51 may include silicon oxide, but is not limited thereto. The material of the second initial mask layer 52 may include silicon nitride, but is not limited thereto.
At S300: a plurality of columns of silicon pillar structures and support structures are formed in the stack structure located on the second area. The plurality of columns of silicon pillar structures are arranged at intervals in a first direction. Each column of silicon pillar structure includes a plurality of silicon pillars that are arranged at intervals and are parallel to the substrate. The plurality of silicon pillars in the plurality of columns of silicon pillar structures are distributed in a plurality of layers. The support structure is configured to connect any adjacent silicon pillar.
In a possible example, at S310: part of the stack structure is etched to form a plurality of first trenches arranged at intervals in the first direction. The stack structure is divided into a plurality of columns of strips by the plurality of first trenches. Each column of strip includes silicon layers and first sacrificial layers stacked alternately. The length direction of the first trenches is perpendicular to the first direction. The structure is as shown in
Exemplarily, referring to
The first direction is the Y direction in
Referring to
That is to say, the remaining first initial sacrificial layer 22 constitutes a first sacrificial layer 24, and the remaining initial silicon layer 21 constitutes a silicon layer 23, so that the each column of strip 25 includes silicon layers 23 and first sacrificial layers 24 that are stacked and arranged alternately. The remaining initial mask layer 50 forms a plurality of columns of mask layers 55. A plurality of columns of mask layers 55 and a plurality of columns of strips 25 are arranged in one-to-one correspondence. Each column of mask layers 55 includes a first mask layer 53 and a second mask layer 54 stacked and arranged alternately.
At S320: a second sacrificial layer is formed in each of the first trenches.
Referring to
Exemplarily, the second sacrificial layer 80 is formed in the first trenches 70 by the processes such as a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, or an Atomic Layer Deposition (ALD). The thickness direction of the second sacrificial layer 80 and the depth direction of the first trench 70 are the same and both are a direction perpendicular to the substrate 10.
In the embodiment, the material of the second sacrificial layer 80 includes silicon oxide, but is not limited thereto.
At S330: part of the second sacrificial layer is etched to form a plurality of second trenches in the second sacrificial layer. The second trenches expose part of the top surface of the substrate. Moreover, part of the first sacrificial layer is removed to form a plurality of third trenches arranged at intervals in the first sacrificial layer. The third trenches are communicated with the second trenches to form a filling area.
Exemplarily, referring to
After that, referring to
Taking the orientation shown in
In the first direction, side walls of each second trench 81 are opposite surfaces of adjacent columns of strips 25. Thus, each second trench 81 exposes part of the first sacrificial layer 24, so that part of the first sacrificial layer 24 can be selectively removed subsequently, which ensures the normal progress of a process for manufacturing the semiconductor structure.
After that, referring to
Finally, the second photoresist layer 90 and the second sacrificial layer 80 located on the mask layer 55 may be removed.
At S340: support structures are formed in the filling area. The support structure includes a plurality of support pillars arranged in a rectangular array. Each support pillar is configured to connect adjacent silicon pillars.
Exemplarily, referring to
After that, the insulating layer 41 located on the top surfaces of the strips 25 and the mask layers 55 is removed through a Chemical Mechanical Polishing (CMP) process, so as to expose the top surfaces of the mask layers 55.
Referring to
At S350, the remaining first sacrificial layer and the remaining second sacrificial layer located on the second area are removed to form a plurality of columns of silicon pillar structures.
Exemplarily, referring to
After that, referring to
It is to be noted that the silicon layer 23 located above the second area may be referred to as a silicon pillar 31, and the silicon layer 23 located above the first area is configured to form an active pillar. In addition, the remaining first mask layer 53 located on the silicon layer 23 also needs to be removed at this step.
At S400, a capacitor structure surrounding each of the silicon pillars is formed.
Exemplarily, referring to
In an example, a metal with a certain thickness may be selectively formed on each of the silicon pillars 31 through a selective Conductive on Conductive (CoC) ALD process, so as to form a first electrode layer 111. Thus, the area defined by the silicon pillar 31 and the support structure 40 may be prevented from filling up with the metal, and thus it is avoided that part of the metal needs to be removed by an etching process, so that a process for manufacturing a capacitor structure can be simplified, thereby reducing the production cost of the process for manufacturing the semiconductor structure.
In the embodiment, the dielectric layer 112 has a high dielectric constant, so that the performance of the capacitor structure can be ensured. A material with a high-k dielectric constant may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), lanthanum oxide (LaO), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTiO3), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), lithium oxide (Li2O), aluminum oxide (Al2O3), lead scandium tantalum oxide (PbScTaO), lead zinc niobate (PbZnNbO3), or combinations thereof.
During forming the capacitor structure, by the provision of the support structure 40, the silicon pillar 31 may be supported in both the horizontal plane and the vertical plane, so that the bearing capacity of the silicon pillar 31 is improved, preventing the silicon pillar 31 i from deforming due to the pressure of the capacitor structure 110, thereby improving the yield of the semiconductor structures.
In some embodiments, after the step in which the capacitor structure surrounding each silicon pillar is formed, the method for manufacturing the semiconductor structure further includes the following operation.
Referring to
The first interconnection layer is configured to connect the second electrode layers 113 of all capacitor structures together, so that all of the capacitor structures are arranged in parallel. Therefore, the capacitance of the semiconductor structure is the sum of the capacitances of all of the capacitor structures, and the total current after the capacitor structures are connected in parallel is equal to the sum of the current of the capacitor structures. Thus, the storage capacity of the semiconductor structure can be increased, and thus the performance of the semiconductor structure is improved.
After that, referring to
Referring to
Referring to
After that, referring to
In this step, the epitaxial layer may be oxidized directly by a high-temperature oxidization treatment process in deposition equipment. Thus, the volume of the second gap can be reduced, thereby better ensuring the electrical insulation between the plurality of capacitor structures located on a same silicon pillar.
In the embodiment, the thickness of the oxide layer is greater than that of the first electrode layer 111 and is less than the sum of the thicknesses of the first electrode layer 111 and the dielectric layer 112. Thus, a space can be reserved for the formation of the second interconnection layer 170, which ensures the interconnection of the second electrode layers 113 of the capacitor structures 110, and can also ensure the electrical insulation between the plurality of capacitor structures 110 located on the same silicon pillar 31.
It is to be noted that before the step in which the epitaxial layer is oxidized, the remaining first mask layer located on the first area may also be removed.
After the epitaxial layer 140 and the oxide layer 160 are formed, referring to
In the embodiment, the plurality of capacitor structures can be arranged in parallel through providing the first interconnection layer 130 and the second interconnection layer 170, so that the storage capacity of the capacitor structure is increased, and thus the performance of the semiconductor structure is improved.
In some embodiments, after the step in which the second interconnection layer is formed, the method for manufacturing the semiconductor structure further includes the following operation.
The first sacrificial layer in the stack structure located on the first area is removed. Exemplarily, a third photoresist layer (not shown in the drawings) is formed on the semiconductor structure located on the second area, and then the first sacrificial layer 24 located on the first area is removed by an etching gas or an etching liquid, so as to expose the silicon layer 23 located on the first area.
After that, an active pillar is formed in the silicon layer located on the first area. The active pillar includes a channel, and a source and a drain located on either side of the channel. The types of doping ions of the source and the drain may be the same, and the type of the doping ions of the channel may be different from that of the source. In an example, the doping ions of the channel may be P-type ions, and the doping ions of the source and drain may be N-type ions. In another example, the doping ions of the channel may be N-type ions, and the doping ions of the source and the drain may be P-type ions.
In the embodiment, the source, the drain, and the channel of the active pillar may be formed in segments through an ion diffusion or Plasma Doping System (PALD) process.
The process for forming the active pillar is not limited to the above description. The active pillar may also be formed by the following process steps: exemplarily, a fourth photoresist layer (not shown in the drawings) may be formed on the semiconductor structure located in the second area and part of the stack structure located in the first area. The fourth photoresist layer can block part of the stack structure and the semiconductor structure located on the second area. Then, part of the first sacrificial layer in the stack structure located on the first area is removed by dry etching or wet etching, so as to expose part of the silicon layer located on the first area. Then, part of the silicon layer located on the first area is exposed for ion doping by a plasma doping process, so as to form a channel. After that, the fourth photoresist layer is removed and a fifth photoresist layer covering the channel is formed. After that, the remaining first sacrificial layer is removed by dry etching or wet etching to expose the remaining silicon layer on the first area. After that, the remaining silicon layer located on the first area is exposed for ion doping by a plasma doping process, so as to form the source and drain. It is to be noted that a source and a drain may also be formed first by the abovementioned process, and then the channel is formed. The forming sequence of the source, the drain, and the channel of the active pillar is not specifically limited in the embodiment.
After the active pillar is formed, a plurality of bit lines 190 and a plurality of word lines 180 are formed on the first area. Reference can be made to
A plurality of bit lines 190 are arranged at intervals in the first direction. Each bit line 190 extends in the direction perpendicular to the substrate 10 and connects the active pillars in a same column. In an example, the bit line 190 may connect the sources of the active pillars in the same column. Correspondingly, the capacitor structure 110 may be connected to the drain of the active pillar. In another example, the bit line 190 may connect the drains of the active pillars in a same column. Correspondingly, the capacitor structure 110 may be connected to the source of the active pillar.
A plurality of word lines 180 are arranged at intervals in the direction perpendicular to the substrate 10. Each word line 180 extends in the first direction and connects the active pillars in a same layer. That is, each word line 180 is configured to connect the channels of the active pillars in the same layer.
In order to realize the insulation arrangement between adjacent bit lines 190 and word lines 180, the method for manufacturing a semiconductor structure further includes that: isolation layers 210 wrapping each bit line 190 and each word line 180 are formed on the first area. The material of the isolation layer 210 may include silicon oxide or silicon nitride.
The embodiments of the disclosure further provide a semiconductor structure. Reference is made to
Various embodiments or implementation modes in the specification are described in a progressive mode. Each embodiment focuses on differences from other embodiments, and the same and similar parts of various embodiments may be referred to one another.
In the description of the specification, the description referring to the terms “one implementation mode ” “some implementation modes”, “schematic implementation mode”, “example”, “specific example”, or “some examples” etc. means that the specific features, structures, materials, or characteristics described in combination with the implementation modes or examples are included in at least one implementation mode or example of the disclosure.
In the specification, the schematic expression of the above terms does not necessarily mean the same implementation mode or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in an appropriate mode in any one or more implementation modes or examples.
Finally, it is to be noted that the foregoing embodiments are merely intended for describing the technical solutions of the disclosure, instead of limiting the disclosure. Although the disclosure is described in detail with reference to the foregoing embodiments, persons of ordinary skill in the art should understand that they may still make modifications to the technical solutions described in the foregoing embodiments or make equivalent replacements to some or all technical features thereof, without departing from the scope of the technical solutions of the embodiments of the disclosure.
Number | Date | Country | Kind |
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202210447115.X | Apr 2022 | CN | national |
This application is a U.S. continuation application of International Application No. PCT/CN2022/108345, filed Jul. 27, 2022, which claims priority to Chinese Patent Application No. 202210447115.X, filed Apr. 26, 2022. International Application No. PCT/CN2022/108345 and Chinese Patent Application No. 202210447115.X are incorporated herein by reference in their entireties.
Number | Date | Country | |
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Parent | PCT/CN2022/108345 | Jul 2022 | WO |
Child | 18152193 | US |