BRIEF DESCRIPTION OF THE DRAWINGS
In drawings which illustrate embodiments of the invention,
FIG. 1 is a schematic cross sectional view of a semiconductor apparatus in accordance with a first embodiment of the invention;
FIG. 2 is a perspective view of the semiconductor structure shown in FIG. 1;
FIG. 3 is a plan view of the semiconductor structure shown in FIG. 1 in accordance with an alternative embodiment of the invention;
FIG. 4 is a plan view of the semiconductor structure shown in FIG. 1 in accordance with an alternative embodiment of the invention;
FIG. 5 is a plan view of the semiconductor structure shown in FIG. 1 in accordance with an alternative embodiment of the invention;
FIG. 6 is a schematic cross sectional view of a semiconductor structure in accordance with a second embodiment of the invention;
FIG. 7 is a schematic cross sectional view of a semiconductor apparatus in accordance with an embodiment of the invention including the semiconductor structure shown in FIG. 6;
FIG. 8 is a perspective view of the semiconductor apparatus shown in FIG. 7, showing electrodes being connected to the semiconductor structure; and
FIGS. 9-15 are a series of schematic cross-sectional views illustrating a process for producing the semiconductor structure shown in FIG. 7, in accordance with an embodiment of the invention.
DETAILED DESCRIPTION
Referring to FIG. 1, a semiconductor apparatus in accordance with a first embodiment of the invention is shown generally at 100. The semiconductor apparatus 100 includes a first doped volume 102 of semiconductor material, having a front surface 104. The first doped volume 102 includes a first region 106 having a first concentration of dopant and a first exposed area 111 on the front surface 104. The first concentration of dopant causes the first region 106 to have a first polarity type such as n-type, for example. The first doped volume 102 also includes a second region 108 adjacent the first region 106. The second region 108 has a second concentration of the same dopant used to dope the first region 106 and has a second exposed area 110 on the front surface 104. The concentration of dopant in the second region 108 is higher than the concentration of dopant in the first region 106 and causes the second region 108 to have the same polarity type as the first region. Where n-type dopants are used, to distinguish between these two regions the first region may be designated as an n region and the second region may be designated an n+ region.
In one embodiment the first doped volume 102 includes n-type dopant elements in a concentration sufficient to cause the first region 106 to have a sheet resistance of between about 80 ohms/sq to about 150 ohms/sq. The concentration of dopant in the second region 108 is selected to cause the second region to have a sheet resistance of between about 0.5 ohms/sq and about 40 ohms/sq.
In the embodiment shown the second region 108 extends through the first region 106, however in other embodiments (not shown) the second region 108 may extend only partway through the first region 106, or may extend beyond the first region into an adjacent doped volume of semiconductor material, as shown later herein. A boundary 109 exists between the first region 106 and the second region 108. This boundary 109 may be referred to as an isotype junction to indicate that the junction is between semiconductor materials having a common polarity type.
The semiconductor apparatus 100 further includes a first external conductor 112. The first external conductor 112 is bonded to the second exposed area 110 by an alloy 114. The alloy 114 facilitates ohmic connection between the first external conductor 112 and the second region 108.
In one embodiment the alloy 114 includes an alloy of indium (In), tin (Sn), and silver (Ag) in a proportion of about 47% In, about 51% Sn, and about 2% Ag, and has a thickness of between about 1 micron and about 5 microns. In another embodiment the alloy 114 includes an alloy of indium (In) and tin (Sn) in a proportion of about 48% In to about 52% Sn. In other embodiments the alloy 114 may include two or more of the following metals: silver (Ag), bismuth (Bi), cadmium (Cd), gallium (Ga), indium (In), lead (Pb), antimony (Sb), tin (Sn), and zinc (Zn), for example. In general, the metals included in the alloy 114 are selected to cause the alloy to have a melting temperature of between about 30 degrees Celsius and about 200 degrees Celsius, and more particularly, a melting temperature of between about 60 degrees Celsius and about 150 degrees Celsius.
The first external conductor 112, in this embodiment, includes a wire of rectangular cross section, but in other embodiments the conductor may have a generally circular or triangular cross section. The first external conductor 112 may include a metal wire such as silver or copper, or alloys thereof, for example, and the conductor may have a diameter of between about 30 microns and 300 microns.
Referring to FIG. 2, in one embodiment, the second exposed areas 110 of the plurality of separate second regions 108 may be arranged in a plurality of parallel rows 160 and columns 200, each row and column including a plurality of generally rectangular second exposed areas 110. Each of the second exposed areas 110 has a second region 108 (shown in FIG. 2) underlying the second exposed areas. The second exposed areas 110 are surrounded by the first exposed area 111, and the first region 106 underlies the first exposed areas.
The second exposed areas 110 may have a generally rectangular shape and may have a length 202 in the range of approximately 1 millimetre to approximately 10 millimetres, and a width 204 in the range of between about 50 microns to about 150 microns. The columns 200 may be parallel and spaced apart such that a spacing distance 206 between adjacent second exposed areas 110 in the same column is about 1 millimetre to about 3 millimetres and such that a distance 208 between adjacent rows 160 is between about 1 millimetre and about 10 millimetres.
Referring to FIG. 3, in an alternative embodiment the second exposed areas 110 on the front surface 104 may be arranged in a plurality of parallel spaced apart rows 210, and the second exposed areas in adjacent rows may be staggered in a direction shown by arrow 212. In the embodiment shown, a distance 214 between the second exposed areas 110 in the same row is about 1 millimetre to about 3 millimetres, and the second exposed areas in adjacent rows are staggered by a distance 216, which in this embodiment is approximately half of the distance 214.
Referring to FIG. 4, in another embodiment the second exposed areas 110 on the front surface 104 (and the underlying second regions 108) may be elongated to form single parallel spaced apart elongate areas 220 extending across the front surface of the semiconductor apparatus 100. The elongate areas 220 may have a width 222 in the range of about 50 microns to about 150 microns and a distance 224 between adjacent parallel lines may be in the range of about 1 millimetre to about 5 millimetres.
Referring to FIG. 5, in yet another embodiment the semiconductor apparatus 100 shown in FIG. 5 may be further provided with transverse interconnecting regions 138 extending between the second regions 108. The interconnecting regions 138 have a dopant concentration that is approximately equal to the second concentration of dopant in the second regions 108 and each interconnecting region 138 has an exposed area 139 on the front surface 104, to define a square mesh pattern across the front surface 104. In one embodiment the interconnecting regions 138 have a width of between about 50 microns and about 150 microns and are separated by a distance of between about 1 and about 5 millimeters.
Semiconductor Structure
Referring to FIG. 6, a semiconductor structure in accordance with a second embodiment of the invention is shown generally at 120. The semiconductor structure 120 includes a first doped volume 122 having a front surface 129. The first doped volume 122 includes a first region 124 having a first concentration of dopant such as phosphorous that causes it to have an n-type polarity. The first region 124 also has a first exposed area 125 on the front surface 129. The first doped volume 122 further includes a plurality of separate second regions 126 having a second concentration of dopant of the same polarity as the first region 124 (in this case a phosphorous dopant). The separate second regions 126 also have respective second exposed areas 128 on the front surface 129. The second concentration of dopant in each of the second regions 126 is higher than the first concentration of dopant in the first region 124. The first region 124 may thus be designated as an n type semiconductor material while the second regions 126 may be designated as n+ type semiconductor material, indicating that the second regions have a higher concentration of n-type dopant than the first region. In the embodiment shown, there are four separate second regions 126, but in other embodiments there may be fewer or more second regions 126, each having a corresponding second exposed area 128.
In the embodiment shown in FIG. 6, the semiconductor structure 120 further includes a second doped volume 130 adjacent the first doped volume 122. The second doped volume 130 includes a dopant such as boron, which causes the second doped volume to have a polarity opposite to the polarity of the first doped volume 122. The second doped volume may thus be referred to as p-type material. The first and second doped volumes 122 and 130 thus form a p/n junction 134 therebetween.
In this embodiment the plurality of separate second regions 126 form isotype junctions 127 (shown in broken lines) with the first region 124, and the second regions extend through the first region 124 and partway into the second doped volume 130. Accordingly, in this embodiment the p/n junction 134 between the first and second doped volumes 122 and 130 is non-planar and non-uniform since the p/n junction includes areas 136 adjacent the separate second regions 126 that extend into the second doped volume 130.
Back Side Connectors
Still referring to FIG. 6, in the embodiment shown, the second doped volume 130 includes a back surface 132, a third region 140, and a plurality of separate fourth regions 142. The third region 140 has a third exposed area 146. The plurality of separate fourth regions 142 each have a fourth concentration of dopant, the dopant being of the same type as that used to dope the third region, e.g. boron. The fourth concentration of dopant in the fourth regions 142 is higher than the third concentration of dopant in the third region 140 and thus the fourth regions 142 may be designated as p+ type semiconductor material while the third region 14 may be designated as p type semiconductor material.
Each of the fourth regions 142 includes a fourth exposed area 144 on the back surface 132. Isotype junctions 282 are formed between the third and fourth regions 140 and 142. The fourth exposed areas 144 may be arranged in patterns similar to those shown in FIGS. 2-5, on the back surface 132 of the semiconductor structure 120, or the fourth exposed areas 144 may extend across the entire back surface 132.
Ohmic Connections to Semiconductor Structure
Referring to FIG. 7, a semiconductor apparatus in accordance with an embodiment of the invention is shown generally at 180. The semiconductor apparatus 180 includes the semiconductor structure 120 and further includes a plurality of connection layers 182. The connection layers 182 the alloy 114, and a plurality of first external conductors 112. A dielectric layer 184 may be located between the alloy 114 and the second exposed areas 128 of the first doped volume 122. In this embodiment, the dielectric layer 184 is sufficiently thin to permit tunneling of charge carriers through the dielectric layer between the alloy 114 and the second region 126. The dielectric layer 184 may include silicon dioxide (SiO2) or silicon nitride (Si3N4) and may have a thickness of about 2 nanometers or less.
The first external conductors 112 are bonded to the second exposed areas 128 by the alloy 114 such that each respective first conductor is mechanically and electrically connected to the corresponding second region 126, such that a low resistance, substantially ohmic, connection is formed between the first conductors and respective second regions.
Similarly, a plurality of second external conductors 188 may be bonded by the alloy 114 to the fourth exposed areas 144 on the back surface 132 of the semiconductor structure 120.
The first conductors 112 are previously adhered to a surface 194 of a polymeric film 190. In one embodiment the film 190 comprises polyester and has a thickness of between about 6 microns and 100 microns. The first conductors 1112 are adhered to the film 190 by a layer of adhesive 191 on the surface 194. The adhesive layer 191 may have thickness of between about 20 microns and about 200 microns, for example. The adhesive layer 191 may include an adhesive material having thermoplastic properties, such that the adhesive becomes fluid when subjected to a temperature in the range of between about 60 degrees Celsius and about 170 degrees Celsius, and more particularly between about 80 degrees Celsius and about 150 degrees Celsius.
The first conductors 112 with the alloy 114 coated thereon, are adhered to the film 190 in spaced apart relation prior to being connected to the semiconductor structure to form a unitary first electrode 193 which has a conductor surface portion 195 that protrudes from the adhesive layer 191 coated on the surface 194. The film 190 can thus be manipulated to position the first conductors 112 thereon in alignment with the second exposed areas 128 on the front surface 129, prior to melting and pressing the alloy 114 and making the desired electrical contact between the conductor surface portions 195 and the second exposed areas.
Similarly a unitary second electrode 196 may be prepared in the same way by pre-adhering the second conductors 188 to a film 192 such that the second conductors have a conductor surface portion 198 that protrudes from an adhesive layer coated on a surface 197 of the film 192.
The semiconductor apparatus 180, in the embodiment shown, also includes a first passivation layer 186 deposited on at least the first exposed area 125. The first passivation layer may extend across the entire front surface 129 over both the first exposed area 125 and the second exposed areas 128, for example. The first passivation layer 186 may include a dielectric material such as silicon nitride. The dielectric layer 184 may include silicon nitride or silicon dioxide. The dielectric layer 184 and the first passivation layer 186 may be one and the same or applied separately. The semiconductor apparatus 180 may also include a second passivation layer (not shown) on at least the third exposed area 146 of the back surface 132. Again, the second passivation layer may extend across the entire back surface 132 including the third exposed area 146 and the fourth exposed areas 144.
Photovoltaic Apparatus & Operation Thereof
The semiconductor apparatus 180 shown in FIG. 7 may be configured to operate as a photovoltaic device. Charge carriers are generated in the semiconductor apparatus in response to receiving light at the front surface 129, and separated at the p/n junction 134. The charge may be collected through the second and fourth exposed areas correspondingly 128 and 144 and used as a source of energy.
When the semiconductor structure 120 is configured to operate as a photovoltaic device, the passivation layer 186 may include an antireflective coating material to minimize reflection of light at the front surface 129, while simultaneously acting as a passivation layer. Advantageously, in photovoltaic devices collection and generation of charge carriers is most efficient in lightly doped areas, which are not shaded by the first conductors 112 due to their positioning over the second exposed areas 128. Light coupling into the first region 124 is enhanced by the antireflective passivation layer 186, which reduces an amount of light reflected from the front surface 129 and increases the amount of light acting on the p/n junction. For example, in embodiments where the first doped volume includes silicon, more than 30% of the incident light may be reflected and unavailable to act on the p/n junction in the absence of an antireflective passivation layer.
Advantageously, the alloy 114 in combination with the higher doping concentrations in the second and fourth regions 126 and 142 facilitate low resistance ohmic contact to the semiconductor structure 120 without substantial voltage drop occurring at the interfaces between the first and second conductors 112 and 188 and the exposed areas 128 and 144 respectively.
Process-External Conductor Application
A process for connecting the first conductors 112 and the second conductors 188 to the semiconductor structure 120 (shown in FIG. 2) is shown generally at 250 in FIG. 8.
Referring to FIG. 8 the process starts with cleaning of the second exposed areas 128 and the fourth exposed areas 144 (not shown in FIG. 8) to remove oxides and/or other contaminants therefrom. In one embodiment cleaning may involve etching the second and fourth exposed areas 128 & 144 to expose a clean surface area that is free of oxides.
Initially, the first electrode 193 may be curled as shown in FIG. 8 to align a rear edge 262 of the electrode with a rear edge 264 of the semiconductor structure 120. The first electrode 193 is then pressed downwardly onto the front surface 129 to roll out the film 190 and to secure the surface 194 to the front surface 129 of the semiconductor structure 120, such that the protruding conductor surface portions 195 of the first conductors 112 come into contact with successive second exposed areas 128 between the rear edge 264 and a front edge 265.
The second electrode 196 may be secured to the back surface 132 of the semiconductor structure 120 following a process similar to the process described above for securing the first electrode 193.
When the first and second electrodes 193 and 196 are secured to the semiconductor structure 120, the films 190 and 192 cause the first and second conductors 112 and 188 to be pressed into contact with the second and fourth exposed areas 128 and 144 respectively.
The process continues with heating of the apparatus 180 to cause the alloy 114 to at least partially melt. In some embodiments an external pressure may be applied to the first and second electrodes 193 and 196, to cause the first and second conductors 112 and 188 to be pressed into contact with the second and fourth exposed areas 128 and 144 while heating. After the alloy 114 has at least partially melted, the external pressure is maintained while cooling the apparatus 180 to cause the alloy to bond the first and second conductors 112 and 188 to the second and fourth exposed areas 128 and 144 respectively. At the same time, the adhesive layer 191 begins to melt and flow when heat and pressure are applied, tending to uniformly adhere the film 190 and 192 to the first and third exposed areas 111 and 144.
Advantageously the alloy 114 facilitates good ohmic contact between the first conductors 112 and the second regions 126, and/or the second conductors 188 and the fourth regions 142.
The first conductors 112 are, in this embodiment, laid out in parallel spaced apart relation on the surface 194 of the first electrode 193 with a spacing corresponding to the spacing 206 (shown in FIG. 3) between adjacent columns 200 of the second exposed areas 128 on the front surface 129.
In effect therefore, in this embodiment the second regions 126 and second exposed areas 128 are arranged in rows 160 and columns 200 and the first electrode 193 includes first conductors 112 arranged in parallel spaced apart relation such that when the electrode is applied to the front surface 129 of the semiconductor structure 120, the electrical conductors make contact with the second exposed areas 128 in respective columns.
As shown in FIG. 8, the first electrode 193 may also include a plurality of conductors 272, 274, 276, and 278, which are in contact with the first conductors 112 and extend beyond the film 190 and which are terminated in contact with a common bus 268. The conductors 272, 274, 276, and 278 may be continuous extensions of the first conductors 112.
In an alternative embodiment of the process, the rear edge 262 of the first electrode 193 may be aligned with a right hand side edge 266 of the semiconductor structure 120 and rolled out across the front surface 129 in a manner such that the conductors contact the second exposed areas 128 in respective rows of highly doped areas on the front surface 129 of the semiconductor structure 120.
Process for Forming First & Second Regions
A process for forming the semiconductor structure shown in FIG. 2 for use as a photovoltaic device is shown in FIGS. 9 to 15. Referring to FIG. 9, the process begins with a starting semiconductor material, which in this embodiment includes a p-type crystalline silicon semiconductor wafer 300 having a front surface 301, a back surface 303, and a thickness 302 of about 150 to about 300 microns.
Referring to FIG. 10, the crystalline silicon semiconductor wafer 300 is first doped with a phosphorous, an n-type dopant, to create a p/n junction 304. The p/n junction 304 defines a first doped volume (or emitter region) 305 to one side of the junction 304, and a second doped volume (or collector region) 307 to the other side of the junction 304. After doping, the first doped volume 305 has a majority of n-type polarity dopants, while in the second doped volume p-type dopants remain in majority. The first doped volume 305 may have a sheet resistance of about 80 to 150 ohms per square.
Alternatively, where the crystalline semiconductor wafer 300 includes an n-type semiconductor material, the p/n junction 304 may be formed by doping the semiconductor material with boron to create a p-type emitter region having a sheet resistance of about 80 to 150 ohms per square.
Referring to FIG. 11, the front surface 301 of the semiconductor structure shown in FIG. 10 is then coated with antireflective material 306 such as silicon nitride. The antireflective coating 306 may be deposited using plasma enhanced chemical vapour deposition (PECVD) or other suitable methods. The thickness of the antireflective coating 306 may vary depending upon the desired spectral response of the photovoltaic device and an acceptable light reflection level from the front surface 301.
Referring to FIG. 12, the antireflective coating 306 shown in FIG. 11 is then removed in certain areas to create openings 308 in the antireflective coating. The openings 308 may be formed by selectively laser ablating the antireflective coating 306 or by selective plasma etching, for example. The openings 308 expose areas 310 of the first doped volume 305.
Referring to FIG. 13, the semiconductor wafer 300 is then subjected to a second doping step to locally increase a concentration of phosphorous beneath the exposed areas 310. Doping may be accomplished by thermal diffusion or other conventional methods, and defines first and second regions 311 and 312 in the first doped volume 305, where the dopant concentration in the second region 312 is increased with respect to the dopant concentration in the first region 311. The second region may have a sheet resistance of between about 0.5 to about 40 ohms per square. The second region 312 may also extend into the collector region beyond the original p/n junction 304 to form p/n junction portions 318.
The second doping step may leave residual doping material and derivatives such as oxides on the semiconductor wafer surface and these may be cleaned by etching, for example. By performing the steps shown in FIG. 9 to FIG. 13, effectively a semiconductor wafer having high doped second regions 312 that are not covered by the antireflective coating 306 is produced.
Advantageously the second regions 312 have relatively low resistivity and thus act as relatively good conductors for collecting current within the first doped volume 305. The exposed areas 310 above the second regions 312 facilitate good ohmic contact to the first doped volume 305 for extracting current from the semiconductor wafer 300 and delivering it to external metallic conductors thus functioning as current collecting areas. In general, the exposed areas 310 may occupy about 3-5% of the front surface 301 of the semiconductor wafer 300, thereby only minimally shading the first region 311 where photo-generation of charge carriers occurs most efficiently.
The lower doped first regions are covered by the antireflective coating 306 and are able to absorb light more efficiently than the second regions 312 (particularly in the blue spectral region). However, the first regions 311 have higher resistivity than the second regions 312, and are relatively poor electrical conductors and thus less well suited for current collection.
While most charge generation occurs in the first region 311, some charge generation may also occur in areas of the second region proximate the p/n junction portions 318 where the p/n junction is not shaded by an electrical conductor (as shown in FIG. 7 at 112).
Referring to FIGS. 14 and 15, the process may continue with forming of the second doped volume 307 of the semiconductor wafer 300. The semiconductor wafer 300 produced according to the process described in connection with FIGS. 9 to 13, is further subjected to additional doping by boron, for example, on the back surface 303, to increase the doping concentration underlying the back surface. In the embodiment shown in FIG. 14, substantially the entire back surface 303 is subjected to this additional doping to form an isotype junction 320, which acts as a back side current collecting area for the solar cell apparatus. Again, doping may be achieved using diffusion or other conventional methods as described above in connection with FIG. 9 to FIG. 13.
Referring to FIG. 15, in an alternative embodiment for forming the second doped volume 307, doping may be selectively applied to produce a third region 321 and a plurality of fourth regions 322, where a dopant concentration in the fourth regions is higher than a dopant concentration in he third regions. Each fourth region has a corresponding fourth exposed area 324 which facilitates ohmic connection to the fourth regions 322, as described above. The fourth exposed areas 324 may be distributed across the back surface 303 similar to the distribution of the second areas 128 shown in FIGS. 2-5, thus facilitating contact by the second electrode 196 shown in FIG. 7 and FIG. 8.
While specific embodiments of the invention have been described and illustrated, such embodiments should be considered illustrative of the invention only and not as limiting the invention.
Patent Application
20080092944
