SEMICONDUCTOR STRUCTURE, FABRICATION METHOD THEREOF, MEMORY AND MEMORY SYSTEM

TECHNICAL FIELD

The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a fabrication method thereof, a memory and a memory system.

BACKGROUND

Dynamic random access memories (DRAMs) are a type of semiconductor memory device. A DRAM consists of a number of duplicated memory cells, each of which includes a capacitive structure configured to store charge. The capacitive structure can influence the storage capacity of the DRAM.

In an existing DRAM, capacitive structures are usually located in the core region. However, fabrication of capacitor holes in the core region is prone to serious effect of etching load, which can degrade the reliability of the capacitive structures.

SUMMARY

According to one aspect of the present disclosure, a method of fabricating a semiconductor structure is provided. The method may include forming a plurality of capacitor holes extending through a stack of layers in a stacking direction. The stack of layers may include a first region and a second region. The capacitor holes may be located in the first region and the second region. The method may include forming a first electrode layer over inside walls of the capacitor holes. The method may include forming a dielectric layer on a side of the stack of layers in the first region and the second region. The method may include removing at least part of the dielectric layer in the second region. The method may include forming a second electrode layer in the first region and the second region. A portion of the second electrode layer in the first region may be separated from a portion of the second electrode layer in the second region. The first electrode layer may be connected with the second electrode layer in the second region.

In some implementations, the first electrode layer in both the first region and the second region may be separated into individual portions.

In some implementations, the removing at least part of the dielectric layer in the second region may include removing the dielectric layer in the second region to expose the first electrode layer in the second region.

In some implementations, the forming the second electrode layer in both the first region and the second region may include forming the second electrode layer on the side of the stack of layers, the second electrode layer located in the first region and the second region. In some implementations, the forming the second electrode layer in both the first region and the second region may include covering the dielectric layer on a side away from the stack of layers and the exposed first electrode layer. In some implementations, the forming the second electrode layer in both the first region and the second region may include filling the capacitor holes. In some implementations, the forming the second electrode layer in both the first region and the second region may include forming a first trench extending through the second electrode layer on the stack of layers in the stacking direction and extending in a first direction. In some implementations, the first trench may separate the portion of the second electrode layer in the first region from the portion of the second electrode layer in the second region in a second direction. In some implementations, the first direction, the second direction, and the stacking direction may be perpendicular to each other.

In some implementations, the method may include forming at least one second trench extending, in the stacking direction, through the portion of the second electrode layer on the stack of layers in the second region. In some implementations, the at least one second trench may separate the second electrode layer in the second region into multiple disconnected portions.

In some implementations, the stack of layers may include sacrificial layers. In some implementations, before formation of the dielectric layer, the method may include forming a supporting layer on the side of the stack of layers in the first region and the second region with the supporting layer filling up the capacitor holes. In some implementations, before formation of the dielectric layer, the method may include forming a plurality of spacer holes extending through the supporting layer into the stack of layers in the stacking direction. In some implementations, before formation of the dielectric layer, the method may include removing the sacrificial layers to form cavities, the spacer holes being located in the first region and the second region. In some implementations, before formation of the dielectric layer, the method may include removing the portions of the supporting layer outside the capacitor holes. In some implementations, the dielectric layer may be located on the stack of layers in the first region and the second region and covers the inside walls of the cavities and the spacer holes.

In some implementations, the removing at least part of the dielectric layer in the second region may include removing the dielectric layer on the stack of layers in the second region. In some implementations, the removing at least part of the dielectric layer in the second region may include exposing a portion of the first electrode layer in the second region.

In some implementations, the forming the second electrode layer in the first region and the second region may include forming the second electrode layer on the side of the stack of layers, the second electrode layer covering the dielectric layer on the side away from the stack of layers in the cavities and the spacer holes. In some implementations, the forming the second electrode layer in the first region and the second region may include covering the first electrode layer that is exposed. In some implementations, the forming the second electrode layer in the first region and the second region may include forming a third trench extending through the second electrode layer on the stack of layers in the stacking direction and extending in a first direction. In some implementations, the third trench may separate the portion of the second electrode layer in the first region from the portion of the second electrode layer in the second region in a second direction. In some implementations, the first direction, the second direction, and the stacking direction may be perpendicular to each other.

In some implementations, the method may include forming a semiconductor layer on a side of the second electrode layer away from the stack of layers, the semiconductor layer filling up the cavities and the spacer holes. In some implementations, the third trench may extend at least through the semiconductor layer and the second electrode layer in the stacking direction.

In some implementations, the method may include forming a fourth trench extending through the semiconductor layer and the second electrode layer in the stacking direction. In some implementations, the fourth trench may separate the second electrode layer in the second region into multiple disconnected portions.

In some implementations, the method may include forming a plurality of active parts extending in the first direction and spaced at an interval in the second direction on a substrate. In some implementations, the method may include doping the active parts corresponding to the second region with a first concentration. In some implementations, the method may include forming gate structures extending in the second direction. In some implementations, the method may include connecting at least the active parts in the first region. In some implementation, the gate structures may extend through the active parts in the stacking direction and resulting in a plurality of channel structures. In some implementations, the first direction, the second direction, and the stacking direction may be perpendicular to each other. In some implementations, the method may include forming the stack of layers on a side of the substrate proximate to the channel structures.

In some implementations, the method may include doping the active parts in the first region with a second concentration that is lower than the first concentration.

According to another aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure may include a stack structure including a first region and a second region. The semiconductor structure may include a first electrode layer located in the first region and the second region. The first electrode layer may extend through the stack structure in the stacking direction and the first electrode layer may be separated into individual portions. The semiconductor structure may include a dielectric layer located at least in the first region. The semiconductor structure may include a second electrode layer located in the first region and the second region. A portion of the second electrode layer in the first region may be separated from a portion of the second electrode layer in the second region. The first electrode layer may be connected with the second electrode layer in the second region. The first electrode layer and the second electrode layer may have the dielectric layer disposed therebetween in the first region.

In some implementations, the first electrode layer in both the first region and the second region may be separated into individual portions.

In some implementations, the second electrode layer in the second region may be separated into individual portions.

In some implementations, the dielectric layer may be located over the stack structure in the first region and covers the first electrode layer in the first region on a side away from the stack structure. In some implementations, the second electrode layer may be located over the stack structure in the first region and the second region and covers the dielectric layer in the first region on a side away from the first electrode layer and the first electrode layer in the second region on the side away from the stack structure.

In some implementations, the dielectric layer may be located over the stack structure in the first region and may extend through portions of the stack structure in the first region and the second region in the stacking direction. In some implementations, the second electrode layer may be located over the stack structure in the first region and the second region and may cover the dielectric layer on a side away from the first electrode layer.

In some implementations, the stack structure may include multiple stacked spacer layers. In some implementations, the dielectric layer and the second electrode layer may also be located between every two spacer layers adjacent in the stacking direction in the second region and the first region.

In some implementations, the semiconductor structure may include a semiconductor layer located on the side of the second electrode layer away from the dielectric layer in the first region and the second region. In some implementations, between every two adjacent spacer layers in the stacking direction, the second electrode layer may surround the semiconductor layer. In some implementations, the portion of the semiconductor layer in the first region may be separated from the portion of the semiconductor layer in the second region.

According to a further aspect of the present disclosure, a memory is provided. The memory may include a semiconductor structure. The semiconductor structure may include a stack structure including a first region and a second region. The semiconductor structure may include a first electrode layer located in the first region and the second region. The first electrode layer may extend through the stack structure in the stacking direction and being separated into individual portions. The semiconductor structure may include a dielectric layer located at least in the first region. The semiconductor structure may include a second electrode layer located in the first region and the second region. A portion of the second electrode layer in the first region may be separated from a portion of the second electrode layer in the second region. The first electrode layer may be connected with the second electrode layer in the second region. The first electrode layer and the second electrode layer may have the dielectric layer disposed therebetween in the first region. The memory may include a peripheral circuit structure electrically connected with the semiconductor structure.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a flowchart illustrating a method of fabricating a semiconductor structure provided by an example of the present application.

FIGS. 2A to 2J are cross-sectional structural diagrams of a semiconductor structure provided by an example of the present application at different process operations.

FIG. 3A is a cross-sectional structural diagram taken along the C1-C1 line in FIG. 2D.

FIG. 3B is a cross-sectional structural diagram taken along the C2-C2 line in FIG. 2E.

FIG. 3C is a cross-sectional structural diagram taken along the C3-C3 line in FIG. 2F.

FIG. 3D is a cross-sectional structural diagram taken along the C4-C4 line in FIG. 2G.

FIG. 3E is a cross-sectional structural diagram taken along the C5-C5 line in FIG. 2H.

FIG. 3F is a cross-sectional structural diagram taken along the C6-C6 line in FIG. 2I.

FIG. 3G is a cross-sectional structural diagram taken along the C7-C7 line in FIG. 2J.

FIGS. 4A to 4H are some other cross-sectional structural diagrams of a semiconductor structure provided by an example of the present application at different process operations.

FIG. 5A is a cross-sectional structural diagram taken along the D1-D1 line in FIG. 4A.

FIG. 5B is a cross-sectional structural diagram taken along the D2-D2 line in FIG. 4B.

FIG. 5C is a cross-sectional structural diagram taken along the D3-D3 line in FIG. 4C.

FIG. 5D is a cross-sectional structural diagram taken along the D4-D4 line in FIG. 4D.

FIG. 5E is a cross-sectional structural diagram taken along the D5-D5 line in FIG. 4E.

FIG. 5F is a cross-sectional structural diagram taken along the D6-D6 line in FIG. 4F.

FIG. 5G is a cross-sectional structural diagram taken along the D7-D7 line in FIG. 4G.

FIG. 5H is a cross-sectional structural diagram taken along the D8-D8 line in FIG. 4H.

FIG. 6A is a cross-sectional structural diagram of another semiconductor structure provided by an example of the present application.

FIG. 6B is a cross-sectional structural diagram taken along the d-d line in FIG. 6A.

FIG. 7 is a structural diagram of a system provided by an example of the present application.

FIG. 8 is a structural diagram of a memory provided by an example of the present application.

FIG. 9 is a cross-sectional structural diagram of a memory provided by an example of the present application.

DETAILED DESCRIPTION

The present application will be described in detail hereafter with reference to accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the present application and not to define its scope. Likewise, the following examples are only some, not all, of the examples of the present application, and all other examples obtained by those of ordinary skills in the art without any creative work fall within the scope claimed by the present application.

In the description herein, it is understood that orientation and position relationships indicated by terms “center”, “lateral”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer” and the like are those based on the drawings and only for the purpose of describing the present application and simplifying the description. There is no indication or implication that the devices or elements referred to must have any particular orientations and positions, or be constructed or operated in any particular orientations and positions. As a result, they should not be understood as limitation for the present application. Moreover, the terms “first”, “second” etc. are only used for the purpose of description and should not be understood to indicate or imply relative importance or to designate the number of the referenced technical features implicitly. Therefore, a feature qualified by “first” or “second” may include explicitly or implicitly one or more instances of the feature.

In the description herein, it is noted that terms “mount”, “interconnect” and “connect” should be explained broadly, unless otherwise specified or limited expressly. They include, for example, fixed connection, removable connection or integral connection; mechanical connection or electrical connection; direct interconnection or interconnection with intermediate medium; or inner communication of two elements. The specific meaning of the above-mentioned terms in the present application will be understood by those of ordinary skills in the art depending on specific circumstances.

It should be understood that the meaning of terms “on,” “over,” and “above” herein should be interpreted in the broadest manner such that “on” not only means “on” something without any intermediate feature or layer (i.e., directly on something) but also includes the meaning of “on” something with an intermediate feature or a layer therebetween.

Terms used herein are only for the purpose of describing examples without any intention of limiting them. Singular forms such as “a”, “an”, and “the” are also intended to include plural forms, unless otherwise noted in the context. The phrase “a plurality of” means two or more. It is also understood that terms “include” and/or “comprise” used herein designate existence of the stated features, integers, steps, operations, units and/or assemblies without excluding existence or addition of one or more other features, integers, steps, operations, units, assemblies and/or any combination thereof.

Examples of the present application provide a semiconductor structure, a fabrication method thereof, a memory and a memory system.

Referring to FIG. 1, a flowchart of a method of fabricating a semiconductor structure provided by an example of the present application is shown. The method of fabricating a semiconductor structure may include, e.g., operations S101-S105.

At operation S101, a plurality of capacitor holes extending through a stack of layers in the stacking direction may be formed. The stack of layers may include a first region and a second region and the capacitor holes are located in both the first region and the second region.

At operation S102, a first electrode layer may be formed over the inside walls of the respective capacitor holes.

At operation S103, a dielectric layer may be formed on a side of the stack of layers in both the first region and the second region.

At operation S104, at least part of the dielectric layer in the second region may be removed.

At operation S105, a second electrode layer may be formed in both the first region and the second region. The portion of the second electrode layer in the first region may be separated from the portion of the second electrode layer in the second region. In the second region the first electrode layer may be connected with the second electrode layer.

It should be understood that the operations shown in the above-described fabrication method are not exclusive and other operations may be performed before, after, or between any one(s) of the shown operations.

Referring to FIGS. 2A to 2J, cross-sectional structural diagrams of a semiconductor structure 10 at different process operations provided by an example of the present application are shown. Referring to FIGS. 4A to 4H, cross-sectional structural diagrams of a semiconductor structure 10 at different process operations provided by an example of the present application are shown. The semiconductor structure 10 may include cup-type capacitive structures or pillar-type capacitive structures. The operations S101-S105 may be further described hereafter with reference to FIGS. 2A to 2J and FIGS. 4A to 4H.

At operation S101, a plurality of capacitor holes Q1 extending through a stack of layers 11 in the stacking direction z are formed. The stack of layers 11 includes a first region AA and a second region BB, and the capacitor holes Q1 are located in both the first region AA and the second region BB.

Here, if the semiconductor structure 10 includes cup-type capacitive structures or pillar-type capacitive structures, referring to the above-mentioned FIGS. 2A to 2D and FIG. 3A, FIG. 3A may be a cross-sectional structural diagram taken along the C1-C1 line in FIG. 2D. The first region AA is the region corresponding to a memory array and the second region BB is used for another purpose. They may adjoin each other, e.g., the second region BB surrounds the first region AA. The capacitor holes Q1 may be distributed throughout the stack of layers 11 and separated from each other. In an example, the capacitor holes Q1 may be disposed to have the same size and arranged at the same interval.

In an example, the stack of layers 11 may be formed using any suitable thin film deposition process, e.g., such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The stack of layers 11 may be composed of alternating stacked layers of different materials, e.g., layers of silicon dioxide and layers of silicon nitride that are stacked alternately.

Two patterning processes that are performed orthogonally or at an angle with respect to each other may be used to form capacitor holes Q1 in both the first region AA and the second region BB of the stack of layers 11. Here, due to the relatively uniform distribution of patterns of the capacitor holes Q1 over the whole surface of the stack of layers 11, the relatively small difference in density of holes between the etching pattern in the first region AA and the etching pattern in the second region BB, the difference in etching depth and size between the capacitor holes Q1 formed in the first region AA and the capacitor holes Q1 formed in the second region BB will be relatively small finally. As such, the effect of etching load may be mitigated and/or avoided. Moreover, even if the effect of etching load occurs to some degree to influence the etching depth and size of the capacitor holes Q1 at the periphery, the effect of etching load will only influence the outermost capacitor holes Q1 in the second region BB, and can hardly influence the capacitor holes Q1 in the first region AA. This is because the second region BB surrounds the first region AA. Therefore, by forming capacitor holes Q1 in both the first region AA1 and the second region BB, the effect of etching load can be mitigated and/or avoided in the first region AA. This may ensure the uniformity in etching depth and size of the capacitor holes Q1 in the first region AA. As such, the phenomenon of some capacitor holes Q1 therein having insufficient etching depths or too small sizes may be avoided.

In some implementations, referring to FIG. 6A, a cross-sectional structural diagram of another semiconductor structure 20 provided by an example of the present application is shown. Referring to FIG. 6B, a cross-sectional structural diagram taken along the d-d line in FIG. 6A is shown. Here, the semiconductor structure 20 includes a first stack structure 21 and a second stack of layers 22 located over the first stack structure 21. The first stack structure 21 includes channel structures 211. The second stack of layers 22 includes a core region aa having capacitor holes q therein and a non-core region bb. In an example, the capacitor holes q can be formed directly in the core region aa. Then, a first electrode layer, a dielectric layer, and a second electrode layer may be fabricated to obtain the capacitive structures in the core region aa.

However, since no capacitor hole q needs to be fabricated in the non-core region during the fabrication of capacitor holes q, there is a large difference in the density of holes between the etching pattern of the core region aa and the etching pattern of non-core region bb. As a result, the undesirable effect of etching load may occur at the boundary between the core region aa and the non-core region bb. This may lead to an obvious difference in etching depth and size between the capacitor holes q at the periphery of the core region aa and the capacitor holes q at the center of the core region aa. For example, the etching depths of the capacitor holes q at the periphery of the core region aa may be too small to make the holes extend through the stack of layers 22 in the stacking direction z. Thus, the capacitive structures formed finally at the periphery of the core region aa may fail to be electrically connected with the corresponding channel structures 211. Additionally and/or alternatively, the sizes of those capacitor holes q may be too small and affect subsequent formation of the corresponding capacitive structures and the reliability of those capacitive structures. However, the semiconductor structure 10 provided by examples of the present application solves the above-mentioned problems at least partially.

It is to be noted that, in the semiconductor structure 10 provided by examples of the present application, capacitive structures may be formed after formation of channel structures. That is, with continued reference to FIGS. 2A to 2D, before the above-mentioned operation S101, the fabrication method may further include the following operations

In some implementations, before the above-mentioned operation S101, the method may include forming a plurality of active parts 122 extending in the first direction x and spaced at an interval in the second direction y on a substrate 121. In some implementations, before the above-mentioned operation S101, the method may include doping the active parts 122 corresponding to the second region BB with a first concentration. In some implementations, before the above-mentioned operation S101, the method may include forming gate structures 123 extending in the second direction y and connecting at least the active parts 122 in the first region AA. The gate structures 123 may extend through the active parts in the stacking direction z and may result in a plurality of channel structures 122a. The first direction x, the second direction y, and the stacking direction z may be perpendicular to each other. In some implementations, before the above-mentioned operation S101, the method may include forming a stack of layers 11 on the side of the substrate 121 proximate to the channel structures 122a.

Here, still referring to FIGS. 2A to 2C, if the semiconductor structure 10 includes cup-type capacitive structures or pillar-type capacitive structures, the substrate 121 may include at least one of single crystal silicon (Si), single crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or any other semiconductor materials known in the art. The first direction x and the second direction y may be the directions in which the stack of layers 11 extend, and may be perpendicular to the stacking direction z of the stack of layers 11. Each of the gate structures 123 may include a gate spacer layer 1231 and a gate layer 1232. The gate spacer layer 1231 may include oxide or any other insulating material, and the gate layer 1232 may include any one or combination of tungsten, cobalt, copper, aluminum, polysilicon and doped crystal silicon.

In an example, the active parts 122 may be formed by etching the substrate 121, and the gate structures 123 adjacent in the first direction x may be separated, and thus, electrically insulated from each other by the insulating material filled therebetween. After the filling of the insulating material, the portion of the substrate 121 other than the active parts 122 (e.g., the bottom portion of the substrate 121) may be removed, and bit lines are fabricated to be connected with the channel structures 122a.

It is to be noted that gate structures 123 may be formed at corresponding locations in the first region AA and the second region BB (e.g., as shown in the above-mentioned FIGS. 2C and 2D) or only at corresponding locations in the first region AA and the present application is not limited in this respect. The active parts 122 corresponding to the second region BB may be doped, which aims to increase the conductivity of those active parts 122.

In some implementations, before formation of the gate structures 123, the fabrication method may further include doping the active parts 122 in the first region AA with a second concentration that is lower than the first concentration. In some implementations, the doping can be performed after formation of the gate structures 123, e.g., doping the channel structures 122a with the second concentration.

Here, the active parts 122 (or the channel structures 122a) in the first region AA are doped mainly to increase the conductivity of the active parts (or the channel structures 122a) in the first region AA, and thus form the corresponding source areas to be electrically connected with the capacitive structures, which may then be formed subsequently.

At operation S102, a first electrode layer 13 may be formed over the inside walls of the respective capacitor holes Q1. Here, referring to FIG. 2D, FIG. 2E, and FIG. 3B, if the semiconductor structure 10 includes cup-type capacitive structures or pillar-type capacitive structures, FIG. 3B may be a cross-sectional structural diagram taken along the C2-C2 line in FIG. 2E. The first electrode layer 13 may include metal or any other conductive material, e.g., such as tungsten or copper. A layer of conductive material may be formed on a side of the stack of layers 11. Then, the portions of the layer of conductive material outside the capacitor holes Q1 may be removed to obtain the first electrode layer 13 located in the respective capacitor holes Q1.

Since the capacitor holes Q1 in the first region AA are separated from each other, as are the capacitor holes Q1 in the second region BB, the first electrode layer 13 in the first region AA is separated, as is the first electrode layer 13 in the second region BB. In other words, the first electrode layer 13 in the first region AA and the first electrode layer 13 in the second region BB both include multiple segmented parts, which are disconnected from each other.

At operation S103, a dielectric layer 14 may be formed on the side of the stack of layers 11 in both the first region AA and the second region BB. Here, the material of the dielectric layer 14 has a high dielectric constant. For different types of capacitive structures, different operations may be taken to form the dielectric layer 14. The operations are mainly different in the specific location of the resulting dielectric layer in first region AA and the second region BB.

In some implementations, if the semiconductor structure 10 includes cup-type capacitive structures, FIG. 3C may be a cross-sectional structural diagram taken along the C3-C3 line in FIG. 2F. In an example, after formation of the first electrode layer 13, a dielectric layer 14 may be formed to cover not only the first electrode layer 13 on the side away from the stack of layers 11, but also the top of the stack of layers 11.

In some implementations, the semiconductor structure 10 may include pillar-type capacitive structures. For example, FIGS. 4A to 4H, some other cross-sectional structural diagrams of a semiconductor structure 10 at different process operations provided by an example of the present application are shown. FIG. 5A is a cross-sectional structural diagram taken along the D1-D1 line in FIG. 4A. FIG. 5B is a cross-sectional structural diagram taken along the D2-D2 line in FIG. 4B. FIG. 5C is a cross-sectional structural diagram taken along the D3-D3 line in FIG. 4C.

In an example, for pillar-type capacitive structures, after formation of the first electrode layer 13, the stack of layers 11 may be partially removed and then the dielectric layer 14 is formed. That is, the stack of layers 11 may include sacrificial layers 112.

In some implementations, before the above-mentioned operation S103, the fabrication method may include forming a supporting layer 15 on the side of the stack of layers 11 in both the first region AA and the second region BB with the supporting layer 15 filling up the capacitor holes Q1. In some implementations, before the above-mentioned operation S103, the fabrication method may include forming a plurality of spacer holes Q2 extending through the supporting layer 15 into the stack of layers 11 in the stacking direction z, and removing the sacrificial layers 112 to form cavities Q3. The spacer holes may be located in both the first region AA and the second region BB. In some implementations, before the above-mentioned operation S103, the fabrication method may include removing the portions of the supporting layer 15 outside the capacitor holes Q1.

Here, the stack of layers 11 may include alternating spacer layers 111 and sacrificial layers 112. The sacrificial layers 112 may include silicon dioxide, and the spacer layers 111 may include silicon nitride. The material of the supporting layer 15 may be different from that of the stack of layers 11. The material of the supporting layer 15 may include, e.g., carbon. The supporting layer 15 not only fills up the capacitor holes Q1 but also cover the top of the stack of layers 11.

In an example, the spacer holes Q2 may be formed by multiple etching operations. For example, a pattern of holes corresponding to the spacer holes Q2 may be formed through the supporting layer 15 and the adjacent spacer layer 111 using a mask. Then, the sacrificial layer 112 may be removed through the pattern of holes by wet etching or dry etching to partially expose the underlying adjacent spacer layer 111. Subsequently, the exposed portions of the underlying spacer layer 111 may be etched to expose the underlying adjacent sacrificial layer 112. The underlying sacrificial layer 112 may be removed from the exposed locations. Through the multiple etching operations, all the sacrificial layers 112 in the stack of layers 11 may be removed such that the spacer layer 111 at the bottom is left. In this way, spacer holes Q2 extending through the supporting layer 15 into the stack of layers 11 in the stacking direction z are obtained.

Meanwhile, during formation of the spacer holes Q2, the sacrificial layers 112 may be removed to obtain the cavities Q3. After formation of the spacer holes Q2 and the cavities Q3, the dielectric layer 14 may be formed such that they are not only located on the stack of layers 11 (e.g., cover the top of the stack of layers 11), but also cover the inside walls of the cavities Q3 and the spacer holes Q2. During the process of removing the sacrificial layers 112 in the stack of layers 11, since the supporting layer 15 is filled into the capacitor holes Q1 to provide support, to maintain the structural integrity of the stack of layers 11. In other words, the stack of layers 11 does not collapse during this process.

It is to be noted that only one cross section shape of each spacer hole Q2 (the shape of circle shown in the figures) and only one arrangement of the spacer holes Q2 are illustrated in the figures, while in other implementations the spacer holes Q2 may each have any other cross section shape (e.g., the shape of trapezoid) and be arranged in any other way without departing from the scope of the present disclosure. Furthermore, the spacer holes Q2 may be formed in any way other than the above-described multiple etching operations, e.g., in a single etching operation.

At operation S104, at least part of the dielectric layer 14 in the second region BB may be removed. Here, for different capacitive structures, different operations may be taken to remove the dielectric layer 14. For example, if the semiconductor structure 10 includes cup-type capacitive structures, with continued reference to FIG. 2F, FIG. 2G, and FIG. 3D (a cross-sectional structural diagram taken along the C4-C4 line in FIG. 2G), the above-mentioned operation S104 may include, e.g., removing the dielectric layer 14 in the second region BB and exposing the first electrode layer 13 in the second region BB.

In an example, for cup-type capacitive structures, the dielectric layer 14 in the second region BB may be removed completely through etching. In other words, the portions of the dielectric layer 14 on the top of the stack of layers 11 and in the capacitor holes Q1 in the second region BB may all be removed. Meanwhile, the first electrode layer 13 in the capacitor holes Q1 in the second region BB may be exposed.

In some implementations, for example, if the semiconductor structure 10 includes pillar-type capacitive structures, with reference to FIG. 4C, FIG. 4D and FIG. 5D (a cross-sectional structural diagram taken along the D4-D4 line in FIG. 4D), the above-mentioned operation S104 may include, e.g., removing the portion of the dielectric layer 14 on the top of the stack of layers 11 in the second region BB and exposing a portion of the first electrode layer 13 in the second region BB.

In an example, for pillar-type capacitive structures, the dielectric layer 14 in the second region BB may be removed partially through etching. In other words, the portion of the dielectric layer 14 on the top of the stack of layers 11 in the second region BB may be removed to expose the first electrode layer at the corresponding locations (at the tops) of the capacitor holes Q1, while the portions of the dielectric layer 14 on the inside walls of the cavities Q3 and the spacer holes Q2 are not removed.

At operation S105, a second electrode layer 16 may be formed in the first region AA and the second region BB, the portion of the second electrode layer 16 in the first region AA may be separated from the portion of the second electrode layer 16 in the second region BB, and the first electrode layer 13 may be connected with the second electrode layer 16 in the second region BB. Here, the first electrode layer 13, the dielectric layer 14 and the second electrode layer 16 together act as capacitive structures (e.g., capable of storing charges). The second electrode layer 16 may include a conductive material, e.g., such as one or more of tungsten, cobalt, copper, aluminum, polysilicon, and/or doped crystal silicon, just to name a few. The portion of the second electrode layer 16 in the first region AA may be separated from the portion of the second electrode layer 16 in the second region BB. This means that the portion of the second electrode layer 16 in the first region AA may be disconnected with the portion of the second electrode layer 16 in the second region BB. In other words, there is no contact area between the second electrode layer 16 in the first region AA and the second electrode layer 16 in the second region BB. The second electrode layer 16 in these two regions are electrically insulated from each other when the device is powered during use. In the second region BB the first electrode layer 13 is connected with the second electrode layer 16, which means that first electrode layer 13 in the second region BB and the second electrode layer 16 in the second region BB are in direct contact at least in some areas, and will be electrically connected with each other when the device is powered during use.

In some implementations, if the semiconductor structure 10 includes cup-type capacitive structures, with continued reference to FIGS. 2G to 2I, FIG. 3E (a cross-sectional structural diagram taken along the C5-C5 line in FIG. 2H), and FIG. 3F (a cross-sectional structural diagram taken along the C6-C6 line in FIG. 2I), the above-mentioned operation S105 may include forming a second electrode layer 16 on the side of the stack of layers 11 in the first region AA and the second region BB, the second electrode layer 16 covering the dielectric layer 14 on the side away from the stack of layers 11 and the exposed first electrode layer 13 and filling up the capacitor holes Q1. In some implementations, the above-mentioned operation S105 may include forming a first trench 171 extending through the second electrode layer 16 on the stack of layers 11 in the stacking direction z and extending in the first direction x. The first trench 171 may separate the portion of the second electrode layer 16 in the first region AA from the portion of the second electrode layer 16 in the second region BB in the second direction y. The first direction x, the second direction y, and the stacking direction z may be perpendicular to each other.

Here, for cup-type capacitive structures, since the dielectric layer 14 in the second region BB is completely removed, the first electrode layer 13 in the second region BB is fully exposed. Moreover, the second electrode layer 16 formed in the second region BB may be in contact and fully connected with the first electrode layer 13 in the second region BB. When the device is powered during use, the first electrode layer 13 and the second electrode layer 16, which are connected, will be short-circuited, and thus, electrically connected. Meanwhile, the portion of the dielectric layer 14 in the first region AA is not removed. Consequently, the first electrode layer 13 and the second electrode layer 16 in the first region AA may be separated from each other by the dielectric layer 14.

The first trench 171 is configured to separate the second electrode layer 16 into two disconnected portions, e.g., the portion of the second electrode layer 16 in the first region AA and the portion of the second electrode layer 16 in the second region BB. As such, the two portions are separated and electrically insulated from each other. Here, the first trench 171 may be correspondingly located at the boundary between the second region BB and the first region AA.

In some implementations, if the semiconductor structure 10 includes cup-type capacitive structures, as shown in FIG. 2H, FIG. 2I, and FIG. 3F, the fabrication method may further include forming at least one second trench 172 extending (in the stacking direction z) through the portion of the second electrode layer 16 over the stack of layers 11 in the second region BB. Here, at least one second trench 172 may separate the portion of the second electrode layer 16 in the second region BB into multiple portions.

Still further, the second trench(es) 172 may be formed via etching and configured to separate the second electrode layer 16 in the second region BB into multiple portions. In other words, multiple portions of the second electrode layer 16 may be disconnected and controlled independently. The first trench 171 and the second trench(es) 172 may be formed via the same etching process or via different etching processes, and there is no limitation on the sequence in which they are formed.

Any one of the portions of the second electrode layer 16 formed by separating in the second region BB may be connected with corresponding disconnected first electrode layer 13. The connected first electrode layer 13 and the second electrode layer 16 may serve (as a whole) as a contact structure M. In this way, multiple contact structures M may be obtained such that they each extend through the stack of layers 11 in the stacking direction z. The number and location(s) of the second trench(es) 172 may be determined based on the number and locations of the contact structures M to be fabricated.

In some implementations, if the semiconductor structure 10 includes pillar-type capacitive structures, as shown in FIGS. 4D to 4G and FIGS. 5E to 5G (FIG. 5E being a cross-sectional structural diagram taken along the D5-D5 line in FIG. 4E, FIG. 5F being a cross-sectional structural diagram taken along the D6-D6 line in FIG. 4F and FIG. 5G being a cross-sectional structural diagram taken along the D7-D7 line in FIG. 4G), the above-mentioned operation S105 may include forming a second electrode layer 16 on a side of the stack of layers 11, the second electrode layer 16 covering the dielectric layer 14 on the side away from the stack of layers 11 in the cavities Q3 and the spacer holes Q2 and covering the exposed first electrode layer 13; and

In some implementations, the above-mentioned operation S105 may include forming a third trench 173 extending through the second electrode layer 16 on the stack of layers 11 in the stacking direction z and extending in the first direction x. The third trench 173 may separate the portion of the second electrode layer 16 in the first region AA from the portion of the second electrode layer 16 in the second region BB in the second direction y. The first direction x, the second direction y, and the stacking direction z may be perpendicular to each other.

Here, for pillar-type capacitive structures, since the portion of the dielectric layer 14 in the second region BB is only partially removed, the first electrode layer 13 in the second region BB is only partially exposed partially (e.g., only exposed at the tops of the capacitor holes Q1). The portion of the second electrode layer 16 formed in second region BB is only in direct contact and connected with the portions of the first electrode layer 13 exposed in the second region BB. Therefore, the first electrode layer 13 and the second electrode layer 16 that are connected in this way will be short-circuited, and thus, electrically connected with each other, when the device is powered on during use.

Meanwhile, the second electrode layer 16 is also filled into the cavities Q3 and the spacer holes Q2. In other words, the second electrode layer 16 exists not only on the top of the stack of layers 11, but also in the cavities Q3 and spacer holes Q2. In contrast to the cup-type capacitive structures without cavities Q3, the pillar-type capacitive structures have increased effective area of the second electrode layer 16 and, in turn, improved capacity of charge storage.

Similar to the function of the first trench 171 for the cup-type capacitive structures, the third trench 173 is configured to separate the second electrode layer 16 into two disconnected portions to isolate the portion of the second electrode layer 16 in the first region AA and the portion of the second electrode layer 16 in the second region BB. This achieves electrical insulation between the portion of the second electrode layer 16 in the first region AA and the portion of the second electrode layer 16 in the second region BB.

In some implementations, for pillar capacitive structures, with continued reference to FIGS. 4E and 4H and FIGS. 5E and 5F, the fabrication method may further include forming a semiconductor layer 18 on the side of the second electrode layer 16 away from the stack of layers 11, the semiconductor layer 18 filling up the cavities Q3 and the spacer holes Q2.

Here, the semiconductor layer 18 covers the second electrode layer 16 on the top of the stack of layers 11 in the first region AA and the second electrode layer BB. Moreover, the semiconductor layer 18 may also fill the cavities Q3 and the spacer holes Q2. The semiconductor layer 18 may include at least one of polysilicon or silicide, e.g., silicon germanium (SiGe). The third trench may be formed after formation of the semiconductor layer 18. Furthermore, since the semiconductor layer 18 is in direct contact (e.g., connected) with the second electrode layer 16, the third trench needs to extend at least through the semiconductor layer 18 and the second electrode layer 16 in the stacking direction z in order to separate the portion of the second electrode layer 16 in the second region BB from the portion of the second electrode layer 16 in the first region AA. Furthermore, if the first electrode layer 13 is further disposed at the corresponding locations of the third trench, the third trench needs to extend further through the first electrode layer 13.

In some implementations, for pillar capacitive structures, with reference to FIGS. 4F, 4G, and 5G, the fabrication method may further include forming a fourth trench 174 extending through the semiconductor layer 18 and the second electrode layer 16 in the stacking direction z to separate the second electrode layer 16 in the second region BB into multiple disconnected portions.

Here, similar to function of the second trenches 172 for the cup-type capacitive structures, the fourth trench 174 is configured to separate the second electrode layer 16 in the second region BB into multiple disconnected portions. Furthermore, if the first electrode layer 13 is further disposed at the location of the fourth trench 174, the fourth trench 174 needs to extend further through the first electrode layer 13.

Any one of the portions of the second electrode layer 16 formed by separating in the second region BB is connected with corresponding separated first electrode layer 13 and semiconductor layer 18. The first electrode layer 13, the second electrode layer 16, and the semiconductor layer 18 that are connected as a whole may serve as a contact structure N, so that multiple contact structures N are obtained with each of them extending through the stack of layers 11 in the stacking direction z.

In some implementations, the semiconductor structure 10 includes cup-type capacitive structures, as shown in FIGS. 2I, 2J, and 3G, where FIG. 3G is a cross-sectional structural diagram taken along the C7-C7 line in FIG. 2J. Here, after formation of the first trench 171 and the second trenches 172, a first insulating layer 191 is formed on a side of second electrode layer 16 away from the stack of layers 11. The first insulating layer 191 may fill the first trench 171 and the second trenches 172. Thereafter, a lead-out wiring 192 is formed on the side of the first insulating layer 191 away from the second electrode layer 16 and extends through the first insulating layer 191 in the stacking direction z. In this way, the lead-out wiring 192 reaches and is electrically connected with the second electrode layer 16.

FIGS. 4G, 4H, and 5H illustrate a semiconductor structure 10 that includes pillar-type capacitive structures, according to some implementations of the present disclosure. FIG. 5H is a cross-sectional structural diagram taken along the D8-D8 line in FIG. 2H. Here, after formation of the third trench 173 and the fourth trench 174, a first insulating layer 191 may be further formed on the side of the semiconductor layer 18 away from the stack of layers 11. The first insulating layer 191 fills the third trench 173 and the fourth trench 174. Thereafter, a lead-out wiring 192 is formed on the side of the first insulating layer 191 away from the semiconductor layer 18 and extends through the first insulating layer 191 in the stacking direction z. In this way, the lead-out wiring 192 reaches and is electrically connected with the semiconductor layer 18.

Moreover, the first insulating layer 191 may include an oxide, e.g., silicon dioxide. The lead-out wiring 192 may include a conductive material, e.g., copper. The lead-out wiring 192 may be configured to connect an external host electrically and receive signals therefrom. Similar to the second electrode layer 16, the lead-out wiring 192 may include multiple disconnected portions. This can be considered as the lead-out wiring 192 being separated into individual portions. The disconnected portions of the second electrode layer 16 (or the disconnected portions of the semiconductor layer 18) may be electrically connected with the corresponding disconnected portions of the lead-out wiring 192.

In some implementations, if the semiconductor structure 10 includes cup-type capacitive structures or pillar-type capacitive structures, with continued reference to FIGS. 2J and 4H, after formation of the lead-out wiring 192, a plurality of trenches are formed to extend through the bit lines 124 in the stacking direction z to separate each bit line 124 into multiple disconnected portions, e.g., to separate the bit line 124 internally. The multiple disconnected portions of the bit line 124 are separated from each other at the locations corresponding to those locations, at which the second electrode layer and the semiconductor layer 18 are disconnected, so that each single contact structure M or N can be controlled independently. Thereafter, a second insulating layer 125 is formed on the side of the bit line 124 away from the channel structures 122a. The second insulating layer 125 fills the trenches in the bit lines 124. The second insulating layer 125 may include oxide, e.g., silicon dioxide.

For example, if the semiconductor structure 10 includes cup-type capacitive structures, with continued reference to FIG. 2J, the locations and number of the trenches formed in each bit line 124 correspond to those of the first trench 171 and the second trenches 172 in FIG. 2I. If the semiconductor structure 10 includes pillar-type capacitive structures, with continued reference to FIG. 4H, the locations and number of the trenches formed in each bit line 124 correspond to those of the third trench 173 and the fourth trench 174 in FIG. 3G.

In some implementations, other than the scheme of forming the plurality of trenches extending through the bit lines 124 in the stacking direction z after formation of the lead-out wiring 192, the plurality of trenches extending through the bit lines 124 in the stacking direction z may be formed after formation of the bit lines 124. There is no limitation in this respect. Examples of the present application further provide a semiconductor structure 10 including cup-type capacitive structures or pillar-type capacitive structures. With continued reference to FIG. 2J, FIG. 3G, FIG. 4H, and FIG. 5H, the semiconductor structure 10 may include a stack structure 11a including a first region AA and a second region BB. The semiconductor structure 10 may include the first electrode layer 13 located in the first region AA and the second region BB. The first electrode layer 13 extending through the stack structure 11a in the stacking direction z may be separated into individual portions; a dielectric layer 14 located at least in the first region AA. The semiconductor structure 10 may include a second electrode layer 16 located in the first region AA and the second region BB. The portion of the second electrode layer 16 in the first region AA may be separated from the portion of the second electrode layer 16 in the second region BB. In the second region BB, the first electrode layer 13 may be connected with the second electrode layer 16; and in the first region AA, the first electrode layer 13 and the second electrode layer 16 have the dielectric layer 14 disposed therebetween.

Here, the first direction x and the second direction y may be the directions in which the stack of layers 11 extend, and are perpendicular to the stacking direction z of the stack of layers 11. The first region AA is the region corresponding to a memory array and the second region BB is used for another purpose. They may adjoin each other, e.g., the second region BB surrounds the first region AA. The first electrode layer 13 includes metal or any other conductive material, e.g., such as tungsten or copper. The material of the dielectric layer 14 may have a high dielectric constant. The second electrode layer 16 includes mainly a conductive material, e.g., such as one or more of tungsten, cobalt, copper, aluminum, polysilicon, or doped crystal silicon, just to name a few.

The portion of the second electrode layer 16 in the first region AA is separated from the portion of the second electrode layer 16 in the second region BB, which means that the portion of the second electrode layer 16 in the first region AA is disconnected with the portion of the second electrode layer 16, e.g., there is no contact area therebetween. In the second region BB, the first electrode layer 13 is connected with the second electrode layer 16, which means that the first electrode layer 13 in the second region BB is in direct contact with the second electrode layer 16 in the second region BB, at least in some areas in at least some areas.

The first electrode layer 13 in the first region AA is separated, as is the first electrode layer 13 in the second region BB. In other words, the first electrode layer 13 in the first region AA and the first electrode layer 13 in the second region BB both include multiple segmented parts, which are disconnected from each other.

In some implementations, if the semiconductor structure 10 includes cup-type capacitive structures, with continued reference to FIGS. 2J and 3G, the stack of layers 11 may include alternating spacer layers 111 and sacrificial layers 112. The sacrificial layers 112 may include silicon dioxide and the spacer layers 111 may include silicon nitride.

In some implementations, if the semiconductor structure 10 includes cup-type capacitive structures, with continued reference to FIGS. 2J and 3G, the dielectric layer is located over the stack structure in the first region and covers the first electrode layer in the first region on the side away from the stack structure; and the second electrode layer is located over the stack structure in the first region and the second region, and covers the dielectric layer in the first region on the side away from the first electrode layer and the first electrode layer in the second region on the side away from the stack structure.

In some implementations, if the semiconductor structure 10 includes cup-type capacitive structures, with continued reference to FIGS. 2J and 3G, the semiconductor structure 10 may further include a supporting layer 15 having some portions in the first region AA and the other portions in the second region BB that are separated from each other. The first electrode layer 13 surrounds the supporting layer 15.

The material of the supporting layer 15 is different from that of the stack structure 11a and may be, e.g., carbon.

In some implementations, if the semiconductor structure 10 includes pillar-type capacitive structures, with continued reference to FIGS. 4G and 5G, the dielectric layer 14 is located over the stack structure 11a in the first region AA and extends through portions of the stack structure 11a in the first region AA and the second region BB in the stacking direction z; and the second electrode layer 16 is located over the stack structure 11a in the first region AA and the second region BB and covers the dielectric layer 14 on the side away from the first electrode layer 13.

In some implementations, if the semiconductor structure 10 includes pillar-type capacitive structures, with continued reference to FIGS. 4G and 5G, the stack structure 11a includes multiple stacked spacer layers 111, which are separated from each other in the stacking direction z. The dielectric layer 14 and the second electrode layer 16 are also located between every two spacer layers 111 adjacent in the stacking direction z in the second region BB and the first region AA.

In some implementations, if the semiconductor structure 10 includes pillar-type capacitive structures, with continued reference to FIGS. 4G and 5G, the semiconductor structure 10 may further include a semiconductor layer 18 located on the side of the second electrode layer 16 away from the dielectric layer 14 in the first region AA and the second region BB. Between every two adjacent spacer layers 111, the second electrode layer 16 surrounds the semiconductor layer 18; and the portion of the semiconductor layer 18 in the first region AA is separated from the portion of the semiconductor layer 18 in the second region BB. The semiconductor layer 18 in the second region BB is separated internally.

In some implementations, the semiconductor layer 18 may include at least one of polysilicon or silicide, e.g., silicon germanium (SiGe). The portion of the semiconductor layer 18 in the first region AA is separated from the portion of the semiconductor layer 18 in the second region BB, which means that they are disconnected (e.g., not in direct contact with each other). The portions of the semiconductor layer 18 in the second region BB may be separated, which means that the semiconductor layer 18 in the second region BB is separated into multiple parts that are disconnected (e.g., not in contact with each other).

In some implementations, if the semiconductor structure 10 includes cup-type capacitive structures or pillar-type capacitive structures, with continued reference to FIGS. 2J and 3G, FIG. 4G and FIG. 5G, the semiconductor structure 10 may further include channel structures 122a and gate structures 123. The channel structures 122a may be separated from each other in the first direction x and the second direction y and disposed on the side of the stack structure 11a away from the second electrode layer 16. Each of the gate structures 123 extends in the second direction y and is at least connected with the corresponding channel structure 122a in the first region AA.

The locations of the channel structures 122a correspond to those of the individual portions of the first electrode layer 13. The first direction x, the second direction y, and the stacking direction z are perpendicular to each other. Each of the gate structures 123 may include a gate spacer layer 1231 and a gate layer 1232. The gate spacer layer 1231 may include oxide or any other insulating material. The gate layer 1232 may include, e.g., one or more of tungsten, cobalt, copper, aluminum, polysilicon, and/or doped crystal silicon. The gate structures 123 adjacent in the first direction x may be separated and thus electrically insulated from each other by the insulating material disposed therebetween.

It is to be noted that gate structures 123 may be formed at corresponding locations in both the first region AA and the second region BB, or only at corresponding locations in the first region AA and the present application is not limited in this respect.

In some implementations, if the semiconductor structure 10 includes cup-type capacitive structures or pillar-type capacitive structures, with continued reference to FIGS. 2J and 3G, FIG. 4G and FIG. 5G, the semiconductor structure 10 may further include bit lines 124 located over the channel structures 122a on the side away from the stack structure 11a and connected with the channel structures 122a.

In some implementations, if the semiconductor structure 10 includes cup-type capacitive structures or pillar-type capacitive structures, with continued reference to FIGS. 2J and 3G, FIG. 4G and FIG. 5G, the doping concentration of the channel structures 122a in the second region BB may be different from that of the channel structures 122a in the first region AA and in an example the former is larger than the later.

Here, the larger the doping concentration is, the higher conductivity is. Therefore, the conductivity of the channel structures 122a in the second region BB is higher than that of the channel structures 122a in the first region AA.

It is to be noted that, if the semiconductor structure 10 includes cup-type capacitive structures, with continued reference to FIGS. 2J and 3G, any one of the disconnected portions of the second electrode layer 16 in the second region BB may be connected with corresponding separated first electrode layer 13. The first electrode layer 13 and the second electrode layer 16 that are connected as a whole may serve as a contact structure M. In this way, multiple contact structures M may be obtained with each of them extending through the stack structure 11a to the channel structures 122a in the stacking direction z.

In some implementations, if the semiconductor structure 10 includes pillar-type capacitive structures, with continued reference to FIGS. 4G and 5G, any one of the disconnected portions of the second electrode layer 16 in the second region BB is connected with corresponding separated first electrode layer 13 and semiconductor layer 18. The first electrode layer 13, the second electrode layer 16, and the semiconductor layer 18 that are connected as a whole may serve as a contact structure N, so that multiple contact structures N are obtained with each of them extending through the stack structure 11a to the channel structures 122a in the stacking direction z.

In some implementations, if the semiconductor structure 10 includes cup-type capacitive structures, with continued reference to FIGS. 2J and 3G, the semiconductor structure 10 further includes a first insulating layer 191 and a lead-out wiring 192. Here, the first insulating layer 191 is located on the side of the second electrode layer 16 away from the stack structure 11a and fills up the space between the two adjacent disconnected portions of the second electrode layer 16. The lead-out wiring 192 may be located on the side of the first insulating layer 191 away from the second electrode layer 16, and may extend through the first insulating layer 191 in the stacking direction z to reach and thus be electrically connected with the second electrode layer 16.

In some implementations, if the semiconductor structure 10 includes pillar-type capacitive structures, with continued reference to FIGS. 4G and 5G, the semiconductor structure 10 further includes a first insulating layer 191 and a lead-out wiring 192. The first insulating layer 191 is located on the side of the second electrode layer 16 away from the stack structure 11a and fills up the space between the two adjacent disconnected portions of the second electrode layer 16. The lead-out wiring 192 is located on the side of the first insulating layer 191 away from the semiconductor layer 18 and extends through the first insulating layer 191 in the stacking direction z to reach and thus be electrically connected with the semiconductor layer 18.

Here, the first insulating layer 191 may include oxide, e.g., silicon dioxide. The lead-out wiring 192 may include a conductive material, for example, copper. The lead-out wiring 192 may be configured to connect an external host electrically and receive signals therefrom. Similar to the second electrode layer 16, the lead-out wiring 192 may include multiple disconnected portions such that the lead-out wiring 192 is separated into individual portions. The disconnected portions of the second electrode layer 16 (or the disconnected portions of the semiconductor layer 18) may be electrically connected with the corresponding disconnected portions of the lead-out wiring 192.

It should be understood that for the structures and fabrication processes of the components of the semiconductor structure 10 in examples of the present application, refer to the examples of the fabrication method of the semiconductor structure 10 described above and no repetitions will be made here.

In summary, in the semiconductor structure 10 and the method of fabricating a semiconductor structure 10 provided by examples of the present application, a plurality of capacitor holes Q1 are formed to extend through a stack of layers 11 in the stacking direction z. The stack of layers 11 includes a first area AA and a second area BB, and the plurality of capacitor holes Q1 are distributed in both the first area AA and the second area BB. In this way, the undesirable effect of etching load may be prevented from occurring in the first region AA during formation of the capacitor holes Q1. Moreover, this may ensure the uniformity in size of the capacitor holes Q1 in the first region AA, thereby avoiding under etching. Subsequently, first electrode layer 13 is formed over the inside walls of the capacitor holes Q1, a dielectric layer 14 is formed on the side of the stack of layers in the first region AA and the second region BB. Then, the dielectric layer 14 may be at least partially removed in the second region BB, and a second electrode layer 16 is formed in the first region AA and the second region BB. The portion of the second electrode layer 16 in the first region AA may be separated from the portion of the second electrode layer 16 in the second region BB. In the second region BB, the first electrode layer 13 may be connected with the second electrode layer 16. On one hand, capacitive structures of uniform in size can be formed in the first region AA to improve their reliability; and on the other hand, the first electrode layer 13 and the second electrode layer 16 that are connected in the second region BB may serve as contact structures. As such, there may be no need to fabricate additional contact structures, thereby simplifying the fabrication process is simplified and the flexibility of the process is improved.

Furthermore, referring to FIG. 7, a structural diagram of an example system 100 provided in an example of the present application is shown. The system 100 can be, e.g., a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 7, the system 100 may include a host 101 and a memory system 102 including one or more memories 1021 and a controller 1022. The host 101 may be a processor of an electronic device, such as a central processing unit (CPU) or a memory system on chip (SOC) such as an application processor (AP). The host 101 may be configured to send data to the memory 1021 or receive data from the memory 1021.

In examples of the present application, the memory 1021 is not limited to a 3D DRAM memory and can be implemented as any one of various volatile memories that may lose the data stored therein when powered off, without deviating from the disclosure or teaching of the present application.

In some implementations, the controller 1022 is coupled to the memory 1021 and the host 101 and configured to control the memory 1021, e.g., to control the data write and read operations of the memory 1021. The controller 1022 can manage the data stored in the memory 1021 and communicate with the host 101.

The controller 1022 can be configured to control operations of the memory 1021, such as read, erase, and program operations. The controller 1022 can also be configured to manage various functions with respect to the data stored or to be stored in the memory 1021, including but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc.

The controller 1022 and the one or more memories 1021 can be integrated into various types of storage devices, for example, be included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged into different types of electronic products.

FIG. 8 is a structural diagram of a memory 200 provided in an example of the present application. The memory 200 includes any semiconductor structure 201 described above and a peripheral circuit structure 202 coupled with the semiconductor structure 201. The peripheral circuit structure 202 may be configured to perform read, write, erase, verify and any other operations on the semiconductor structure 201.

In some implementations, the peripheral circuit structure 202 may further include a word line driver, a bit line driver, a column decoder, a sense circuit, a data buffer, a program verify logic, an erase verify circuit and the like, which can perform the above-mentioned operations according to the acquired computer program instructions.

It is noted that the peripheral circuit structure 202 and the semiconductor structure 201 may be arranged in a stack or side by side, without limitation here.

For example, with reference to FIG. 9, which is a cross-sectional structural diagram of a memory 300, the memory 300 includes a semiconductor structure 10 including any cup-type capacitive structures described above and a peripheral circuit structure 301 coupled with the semiconductor structure 10. The peripheral circuit structure 301 and the semiconductor structure 10 are stacked, with the peripheral circuit structure 301 located on the side of the second insulating layer 125 away from the bit lines 124 and electrically connected with the bit lines 124 through contacts.

What have been described above are only examples of the present application and not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present application should be covered by the scope of the present application.

	Number	Date	Country
Parent	PCT/CN2023/094901	May 2023	WO
Child	18372579		US

SEMICONDUCTOR STRUCTURE, FABRICATION METHOD THEREOF, MEMORY AND MEMORY SYSTEM

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CROSS-REFERENCE TO RELATED APPLICATIONS

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