Patent Application
20160181249
The invention relates to semiconductor structures and methods of manufacture and, more particularly, to an integrated FinFET and deep trench capacitor structure and methods of manufacture.
FinFETs are three dimensional structures which provide excellent scalability. For example, FinFETs rise above the planar substrate, giving them more effective gate width for the same substrate footprint than conventional gate structures. Also, by wrapping the gate around the channel, the FET is fully depleted, so that little current is allowed to leak through the body when the device is in the off state, i.e., thereby providing low gate leakage current. This provides superior performance characteristics, e.g., high on currents due to the larger effective gate width, lower off currents due to the full depletion and less threshold voltage variations due to lower channel doping, resulting in improved switching speeds and power.
FinFETs can be fabricated using, for example, silicon on insulator (SOI) substrates. In SOI technologies, FinFETs can be used with many other devices and structures, and can be fabricated using CMOS technologies, e.g., lithography, etching and deposition methods. However because of the three dimensional structure, integration with other devices and/or structures are difficult and quite challenging. For example, it is a challenge to fabricate deep trench capacitors (eDRAM) with current FinFET fabrication processes.
In an aspect of the invention, a method comprises forming a plurality of fin structures from a substrate material. The method further comprises forming a deep trench capacitor structure, contacting at least selected fin structures. The method further comprises forming a liner over the deep trench capacitor structure. The method further comprises forming replacement gate structures with the liner over the deep trench capacitor structure protecting the deep trench capacitor structure during deposition and etching processes.
In an aspect of the invention, a method of forming a deep trench capacitor and a FinFET comprises: patterning semiconductor material to form a plurality of fins along an underlying substrate; segmenting the fins to create a plurality of fin structures with a capping material thereon; forming a deep trench capacitor extending within a buried oxide layer, under the semiconductor material; forming a film of dielectric material over conductive material of the deep trench capacitor; annealing the film of dielectric material thereby hardening the film of dielectric material; and forming replacement gate structures over the plurality of fin structures while protecting the conductor material with the hardened film of dielectric material.
In an aspect of the invention a structure comprises: a plurality of segmented fin structures; a deep trench capacitor extending within a buried oxide layer, under the plurality of segmented fin structures; a hardened film of annealed dielectric material over conductive material of the deep trench capacitor; and replacement gate structures over the plurality of fin structures and at least portions of the hardened film.
The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.
The invention relates to semiconductor structures and methods of manufacture and, more particularly, to an integrated FinFET and deep trench (DT) capacitor structure and methods of manufacture. More specifically, the present invention comprises a method of manufacturing an integrated embedded DRAM (eDRAM) (e.g., deep trench capacitor) with an SOI (silicon-on-insulator) FinFET. The processes include a deep trench (DT) post fin integration process that fully encapsulates poly within the deep trench and prevents it from being attacked by subsequent gate and middle of the line (MOL) processes. In addition, the fins are fully protected during the DT formation process by encapsulating them with a combination of dielectric layers and revealing the fins just before the gate dielectric deposition by etching the dielectric layers encapsulating the fins.
More specifically, in the processes described herein, a DT postfin process provides protection over the deep trench to withstand CMP as well as replacement gate, MOL and other processes. For example, in the formation processes described herein, an encapsulation film (e.g., annealed dielectric material liner) is formed after the deep trench is filled with capacitor material (e.g., poly material). The annealed dielectric material liner will encapsulate or protect the capacitor material during subsequent CMP and wet etch processes. In this way, the processes described herein avoid many issues related to the formation of the fin structures after the DT capacitor structure is formed.
The structures described herein, e.g., deep trench capacitor and FinFETs, can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the structures described herein have been adopted from integrated circuit (IC) technology. For example, the structures of the present invention are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the structures of the present invention uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
In embodiments, the fin structures 18 can be formed using a sidewall image transfer (SIT) technique. In the SIT technique, for example, a mandrel is formed on the semiconductor layer using conventional deposition, lithography and etching processes. A resist is formed on the mandrel material, and exposed to light to form a pattern (openings). A reactive ion etching (RIE) is performed through the openings to form the mandrels. Spacers are formed on the sidewalls of the mandrels which are preferably material that is different than the mandrels, and which are formed using conventional deposition processes known to those of skill in the art. In embodiments, the spacer material can be an oxide film 20 and a nitride film 22, which will remain on the fin structures 18 during subsequent processing steps. The spacers can have a width which matches the dimensions of the narrow fin structures 18, for example. The mandrels are removed or stripped using a conventional etching process, selective to the mandrel material. An etching is then performed within the spacing of the spacers to form the sub-lithographic features, e.g., fin structures 18. In embodiments, the spacer materials, e.g., oxide film 20 and nitride film 22, will remain on the fin structures 18 during subsequent processes.
In embodiments, the fins can be cut or segmented to form a plurality of fin structures 18. For example, by using a conventional lithography and etching processes, .e.g., wet etch process, portions of each fin can be removed to form a plurality of fin structures 18 along a length or width of the substrate 12. This process will be performed pre-cap removal, e.g., prior to removal of the oxide film 20 and nitride film 22.
Still referring to
As shown in
Still referring to
In
As shown in
In
In
The structure then undergoes a thermal anneal process (represented by the plurality of arrows) to harden the high-k dielectric liner 46. In embodiments, the thermal anneal process can be performed at about 400° C. for about 15 minutes. More specifically, the high-k dielectric liner 46, in some embodiments, can be treated to harden and increase the density by baking (i.e., thermal annealing), irradiative annealing, plasma curing, E-beam curing, and/or UV curing the high-k dielectric liner 46. For example, the high-k dielectric liner 46 may be baked (i.e., thermally annealed) at a temperature of up to about 600° C. (e.g., about 300° C. to about 400° C.) for a period of time of up to about an hour (e.g., about 1 minute to about 1 hour).
In
By way of more specific example, a gate dielectric material 54 is deposited on the fin structures 18 using a conventional gate dielectric deposition process. This is followed by deposition and patterning of amorphous silicon to form the gate structure. This is followed by the spacer formation process, e.g., spacer material such as nitride material 58. The process continues with a source-drain epitaxial growth and then the replacement gate process. In embodiments, the material forming the source and drain 60 can be doped Si or other semiconductor material. For example, the source region can be an N+ epi material; whereas, the drain region can be a P+ epi material. In the replacement gate process, the gate amorphous silicon is exposed by a CMP process and the amorphous silicon removed by an isotropic RIE process. This is followed by a deposition of a metal or metal alloy material(s) 56 engineered with certain work functions to form the gate, itself. The structure can then be planarized to remove any excessive gate material, 5followed by contact and anneal processes known to this of skill in the art.
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
