Patent Application
20090080651
This invention relates generally to the protection of intellectual property assets. More particularly, this invention relates to the specification and formation of a semiconductor with hardware locked intellectual property.
Various entities, such as MIPS Technologies, Inc., of Mountain View, Calif. provide solutions to facilitate the design of physical products, such as semiconductors. These solutions, often embodied as computer executable software, are commonly referred to as intellectual property (IP). There are many legitimate transactions that facilitate the rightful use of IP. However, the nature of many forms of IP, for example IP manifested in computer executable software, may result in unlicensed entities utilizing the IP, for example by unauthorized copying of the computer executable software.
Therefore, it would be desirable to provide a mechanism to distribute IP to rightful users while thwarting attempts of unauthorized users from exploiting the IP rights of others.
The invention includes a semiconductor with an intellectual property core with a key check mechanism configured to compare an external key with an internal key in response to a specified event. A pending instruction is executed in response to a match between the external key and the internal key. An unexpected act is performed in response to a mismatch between the external key and the internal key.
The invention also includes a system on a chip with a set of proprietary intellectual property blocks and a key source block. An intellectual property core with a key check mechanism is configured to compare an external key from the key source block with an internal key in response to a specified event. A pending instruction is executed in response to a match between the external key and the internal key. An unexpected act is performed in response to a mismatch between the external key and the internal key.
The invention also includes a computer readable medium with executable instructions to describe an intellectual property core with a key check mechanism configured to compare an external key with an internal key in response to a specified event. A pending instruction is executed in response to a match between the external key and the internal key. An unexpected act is performed in response to a mismatch between the external key and the internal key.
The invention also includes a computer readable medium with executable instructions to describe a set of proprietary intellectual property blocks and a key source block. An intellectual property core with a key check mechanism is configured to compare an external key from the key source block with an internal key in response to a specified event. A pending instruction is executed in response to a match between the external key and the internal key. An unexpected act is performed in response to a mismatch between the external key and the internal key.
The invention also includes a method of producing a system on a chip by delivering an intellectual property core with a key check mechanism. The intellectual property core is combined with a key source block and a set of proprietary intellectual property blocks.
The invention is more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings, in which:
Like reference numerals refer to corresponding parts throughout the several views of the drawings.
A memory 120 is also connected to the bus 114. The memory 120 stores data and executable instructions to implement operations associated with embodiments of the invention. The memory 120 stores an IP core with a key check. The IP core with a key check 120 includes executable instructions to specify a semiconductor core that relies upon a key check mechanism to thwart unauthorized use of the IP core. The semiconductor core may be a microprocessor core, a digital signal processor (DSP) core, and the like. Memory 120 also stores a key source block 124. The key source block 124 includes executable instructions to specify a semiconductor key source that is supplied to the IP core with key check 122. Typically, the key source block is only supplied to a trusted partner, such as a design service firm or semiconductor fabricator. As discussed below, the IP core with key check 122 is only operative with the key source block 124. Therefore, if the IP core with key check 122 is misappropriated, it will be inoperative in the absence of the key source block 124.
The memory 120 may also store a set of proprietary IP blocks, such as IP block_1126 and IP block_N 128. As known in the art, an IP core is typically combined with various proprietary IP blocks so that a customer can produce a system-on-a-chip (SOC) with a desired function. For example, MIPS 1Technologies, Inc., of Mountain View, Calif., provides microprocessor cores that may be combined with proprietary IP blocks to form SOCs used in cable modems, DVD recorders, digital cameras, printers and copiers.
The memory 120 may also include a set of Electronic Design Automation (EDA) tools 130. These tools 130 may include a Register Transfer Level (RTL) synthesizer, a logic analyzer timing analyzer and place and route tools (i.e., silicon compilers). These tools are used to specify an SOC that incorporates the IP core with key check 122, the key source block 124, and the IP blocks 126 and 128.
The next processing operation of
The next processing operation of
The next operation of
In one embodiment, the IP core 302 is configured to include a status register block 400 with storage for a key 402 and/or a seed 404. In one embodiment, the status register block 400 is software configurable to disable the key check mechanism.
In an embodiment utilizing a static value, a static key value 402 is supplied with the IP core 302. The static key value is periodically supplied to a comparison mechanism, such as an Arithmetic Logic Unit (ALU) 408. The ALU also receives a static value from the key source block 304. If the static key from the status register block 400 matches the static key received from the key source block 304 the next pending instruction is processed. If the comparison does not result in a match, then an unexpected action is taken. The unexpected action disrupts the proper operation of the IP core 302 and/or the SOC 300. In an embodiment utilizing a dynamic value, a seed 404 is supplied to a random number generator 406, which periodically supplies dynamic key values to the ALU 408. The key source block 304 includes an identical seed value and random number generator and therefore generates the same sequence of dynamic key values to the ALU 408.
The foregoing operations are more fully appreciated with reference to
If a specified event has occurred (502—YES), then a key match operation is performed 506. If the match is successful (506—YES), then the next instruction is executed 504 and another instruction is fetched 500. If the key match is not successful (506—NO), then an unexpected act is performed 508. The unexpected act is selected to disrupt the proper operation of the IP core 302 and/or the SOC 300. Any number of unexpected acts may be utilized in accordance with the invention. By way of example, not limitation, the following unexpected acts may be taken: perform an incorrect branch, jump to a reset address, invoke a machine check exception, invoke a constant value, invoke a random value, skip an instruction, etc. The unexpected act results in incorrect operation of the IP core 302 and/or the SOC 300. Thus, an entity that has inappropriately pirated the IP core 302 cannot construct a useful SOC. Maintaining a low periodicity for key match comparisons makes it difficult for an unscrupulous entity to debug the problem, while having no meaningful performance impact on licensed users.
The key match comparison operation is more fully appreciated with reference to
In sum, the invention provides a technique to protect IP assets. The technique thwarts unauthorized users of IP by making their chips faulty. The cost of securing authorized rights is lower than the cost of circumventing valid IP rights. Thus, the invention allows IP vendors to distribute their technology more widely without fear of misappropriation.
While various embodiments of the invention have been described above, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant computer arts that various changes in form and detail can be made therein without departing from the scope of the invention. For example, in addition to using hardware (e.g., within or coupled to a Central Processing Unit (“CPU”), microprocessor, microcontroller, digital signal processor, processor core, System on chip (“SOC”), or any other device), implementations may also be embodied in software (e.g., computer readable code, program code, and/or instructions disposed in any form, such as source, object or machine language) disposed, for example, in a computer usable (e.g., readable) medium configured to store the software. Such software can enable, for example, the function, fabrication, modeling, simulation, description and/or testing of the apparatus and methods described herein. For example, this can be accomplished through the use of general programming languages (e.g., C, C++), hardware description languages (HDL) including Verilog HDL, VHDL, and so on, or other available programs. Such software can be disposed in any known computer usable medium such as semiconductor, magnetic disk, or optical disc (e.g., CD-ROM, DVD-ROM, etc.). The software can also be disposed as a computer data signal embodied in a computer usable (e.g., readable) transmission medium (e.g., carrier wave or any other medium including digital, optical, or analog-based medium). Embodiments of the present invention may include methods of providing the apparatus described herein by providing software describing the apparatus and subsequently transmitting the software as a computer data signal over a communication network including the Internet and intranets.
It is understood that the apparatus and method described herein may be included in a semiconductor intellectual property core, such as a microprocessor core (e.g., embodied in HDL) and transformed to hardware in the production of integrated circuits. Additionally, the apparatus and methods described herein may be embodied as a combination of hardware and software. Thus, the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
