Claims
- 1. A sense amplifier having non-inverting and inverting inputs for connection, respectively, to first and second bit lines which, in turn, communicate with at least one MOS memory cell, such amplifier also having an output and comprising:
- a. first through sixth MOS transistors, each having source, drain and gate electrodes;
- b. the non-inverting input being connected to the gate electrodes of the first and second MOS transistors;
- c. the drain electrodes of the first and second MOS transistors being connected to each other and to the gate electrodes of the third and fourth MOS transistors;
- d. the source electrodes of the first and fifth MOS transistors being connected to each other and to the drain electrode of the fourth MOS transistor;
- e. the source electrode of the fourth MOS transistor being connected to ground;
- f. the source electrode of the third MOS transistor being connected to the supply voltage;
- g. the drain electrode of the third MOS transistor being connected to the source electrodes of the second and sixth MOS transistors;
- h. the inverting input being connected to the gates of the fifth and sixth MOS transistors; and
- i. the drain electrodes of the fifth and sixth MOS transistors being connected to each other and to the sense amplifier output.
Parent Case Info
This application is a continuation of application Ser. No. 051,085, filed May 15, 1987, abandoned.
US Referenced Citations (22)
Foreign Referenced Citations (2)
Number |
Date |
Country |
0094574 |
Jul 1981 |
JPX |
0147998 |
Aug 1985 |
JPX |
Continuations (1)
|
Number |
Date |
Country |
Parent |
51085 |
May 1987 |
|