Patent Application
20200322123
The Peripheral Sensor Interface 5 (PSI5) interfaces have a signal called a sync pulse that synchronizes sensors on a communication bus. The sync pulse is a relatively high level/high speed signal that can generate unwanted electro-magnetic emissions from the sensor wires and may cause the restraint module to fail original equipment manufacturer (OEM) electro-magnetic compatibility (EMC) tests.
A restraint control module is provided in this disclosure. The restraint control module is configured to communicate a sync pulse to a sensor. The control module may include a sync pulse driver circuit and a memory. The memory may store the waveform profile of a sync pulse. The sync pulse driver circuit generates a sync pulse in response to the waveform profile stored in the memory. The sync pulse may be transmitted to one or more sensors. The waveform profile stored in the memory may be derived from a sync pulse with reduced electro-magnetic emissions by applying spectrum analysis.
The New Proposed sensor communication control (Sync Pulse) is reshaped via mathematical spectral analysis and subsequent waveform artifact reductions to minimize EMC emissions and provide PSI5 functionality for existing sensors. The control of the sync pulse driver is to provide a DC bias voltage and pulsed value consistent with the existing single-ended solution to be compatible with the existing sensors. Further reductions in EMC emissions beyond the waveshaping can be provided by balanced output impedance and the twisted pair wire communication concept, which all work to attenuate EMC emissions with this newly shaped sync pulse driver concept in a low cost fashion. The reduction in EMC emissions has been measured at 10 dBuV at 100 kHz. This new proposal will provide PSI5 functionality for existing sensors and reduced EMC emissions.
A first line attached to the positive terminal 420 and a second line attached to the negative terminal 422 may be a wire twisted pair. The first line and the second line may have a balanced output impedance. Additionally, the improved sync pulse signal may be symmetrical with respect to time. The improved sync pulse signal may have the same rise and/or fall times as the original PSI5 sync pulse signal. The improved sync pulse signal may have positive initial slope and negative second slope. The improved sync pulse signal may match PSI5 specifications.
To generate the waveform profile, the processor 412 may process an original trapezoidal PSI5 sync pulse signal, for example as shown in
In step 516, an Inverse FFT (IFFT) of Modified_SYNC_Pulse_Data may be performed to obtain a new time domain sync pulse shape [VSYNC_New=IFFT(Modified_SYNC_Pulse_Data)]. One example of the new time domain sync pulse shape is waveform 517. In block, 518 re-shaping of VSYNC_New may be performed to remove ripple voltage prior to the pulse and after the pulse [VSYNC_NewMod1=Reshaped(VSYNC_new)]. One example of the re-shaped sync pulse waveform is waveform 519. In block 520, the DC voltage may be removed to yield the improved sync pulse shape [VSYNC_NewMod1−VDC]. The waveform profile of the improved sync pulse shape may be stored in a memory for use in generating the improved sync pulse in real time by a sync pulse driver. One example of the improved sync pulse shape is waveform 521. In block 522, the improved sync pulse shape may be scaled in time or voltage based on application requirements by the sync pulse driver. Three (3) examples of improved sync pulse shapes scaled in time or voltage amplitude are waveforms 523A, 523B and 523C.
The methods, devices, processing, and logic described above may be implemented in many different ways and in many different combinations of hardware and software. For example, all or parts of the implementations may be circuitry that includes an instruction processor, such as a Central Processing Unit (CPU), microcontroller, or a microprocessor; an Application Specific Integrated Circuit (ASIC), Programmable Logic Device (PLD), or Field Programmable Gate Array (FPGA); or circuitry that includes discrete logic or other circuit components, including analog circuit components, digital circuit components or both; or any combination thereof. The circuitry may include discrete interconnected hardware components and/or may be combined on a single integrated circuit die, distributed among multiple integrated circuit dies, or implemented in a Multiple Chip Module (MCM) of multiple integrated circuit dies in a common package, as examples.
The circuitry may further include or access instructions for execution by the circuitry. The instructions may be stored in a tangible storage medium that is other than a transitory signal, such as a flash memory, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM); or on a magnetic or optical disc, such as a Compact Disc Read Only Memory (CDROM), Hard Disk Drive (HDD), or other magnetic or optical disk; or in or on another machine-readable medium. A product, such as a computer program product, may include a storage medium and instructions stored in or on the medium, and the instructions when executed by the circuitry in a device may cause the device to implement any of the processing described above or illustrated in the drawings.
The implementations may be distributed as circuitry among multiple system components, such as among multiple processors and memories, optionally including multiple distributed processing systems. Parameters, databases, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented in many different ways, including as data structures such as linked lists, hash tables, arrays, records, objects, or implicit storage mechanisms. Programs may be parts (e.g., subroutines) of a single program, separate programs, distributed across several memories and processors, or implemented in many different ways, such as in a library, such as a shared library (e.g., a Dynamic Link Library (DLL)). The DLL, for example, may store instructions that perform any of the processing described above or illustrated in the drawings, when executed by the circuitry.
As a person skilled in the art will readily appreciate, the above description is meant as an illustration of the principles of this disclosure. This description is not intended to limit the scope or application of this disclosure in that the systems and methods are susceptible to modification, variation and change, without departing from spirit of this disclosure, as defined in the following claims.
