Claims
- 1. An electronic circuit for use in comparing two sequences of elements to determine which alignment of the sequences produces the greatest similarity between the sequences, the circuit comprising:
- multiple processors connected in series and individually configured to:
- compare an element in one of the sequences with successive elements in the other sequence,
- for each pair of elements compared, generate a scoring parameter indicating which of a plurality of segments ending at those elements produces the greatest degree of similarity between the sequences,
- use the scoring parameter to generate another scoring parameter for the next pair of elements compared, and
- deliver the scoring parameter to another processor in the series for use in generating another scoring parameter for another pair of elements,
- threshold circuitry configured to determine which processor produces the scoring parameter with the highest value, and
- alignment circuitry configured to determine which alignment of the sequences is associated with the scoring parameter having the highest value.
- 2. The electronic circuit of claim 1, wherein each processor is configured to deliver the scoring parameter to the next processor in the series.
- 3. The electronic circuit of claim 1, wherein all of the processors, except a final processor in the series, are configured to deliver the scoring parameter to another processor.
- 4. The electronic circuit of claim 1, further comprising adjustment circuitry configured to adjust the scoring parameters when two segments differ because one or more deletions appear in one of the segments.
- 5. The electronic circuit of claim 4, wherein the adjustment circuitry is configured to adjust the scoring parameters by a value that depends on which of the segments contains the deletion.
- 6. The electronic circuit of claim 1, further comprising adjustment circuitry configured to adjust the scoring parameters when two segments differ because one or more insertions appear in one of the segments.
- 7. The electronic circuit of claim 6, wherein the adjustment circuitry is configured to adjust the scoring parameters by a value that depends on which of the segments contains the insertions.
- 8. The electronic circuit of claim 1, wherein the processors are configured to generate scoring parameters concurrently and each concurrently generated scoring parameter represents a comparison of segments ending at different elements in the sequences.
- 9. The electronic circuit of claim 1, wherein the sequences are represented as A=a.sub.1, a.sub.2, . . . , a.sub.n, and B=b.sub.1, b.sub.2, . . . , b.sub.m, and wherein each processor is configured to generate the scoring parameter associated with any two elements a.sub.i and b.sub.j, respectively, according to the following equations:
- H.sub.i,j =max{0, H.sub.i-1,j-1 +s(a.sub.i,b.sub.j), E.sub.i,j,F.sub.i,j }
- where E.sub.i,j =max{H.sub.i,j-1 -(U.sub.E,+V.sub.E), E.sub.i,j-1 -V.sub.E}
- F.sub.i,1 =max{H.sub.i-1,j -(U.sub.F +V.sub.F), F.sub.i-1,j -V.sub.F }
- H.sub.i,0 =H.sub.0,j =0
- s(a.sub.i,b.sub.j)>0 if a.sub.i .noteq.b.sub.j
- s(a.sub.i,b.sub.j)<0 if a.sub.i b.sub.j
- and U.sub.E, V.sub.E, U.sub.F and V.sub.F are selected constants.
- 10. The electronic circuit of claim 9, wherein each processor is configured to generate all three values H.sub.i,j, E.sub.i,j, and F.sub.i,j for two elements a.sub.i, b.sub.j.
- 11. The electronic circuit of claim 9, wherein each processor is configured to receive the values H.sub.i-l,j and F.sub.i-l,j from a preceding processor in the series.
- 12. The electronic circuit of claim 9, further comprising a memory device that stores a table from which the values for s(a.sub.i,b.sub.j) are derived.
- 13. The electronic circuit of claim 1, wherein each processor stores a single element from one of the sequences and compares this element to all other elements in the other sequence.
- 14. The electronic circuit of claim 13, wherein each processor generates a scoring parameter for each comparison of the stored element with another element.
Parent Case Info
This is a continuation of application Ser. No. 08/154,633, filed Nov. 18, 1993, now U.S. Pat. No. 5,632,041 which is a continuation of Ser. No. 07,518,562, filed May 2, 1990.
Government Interests
The invention described herein was made in the performance of work under the following contracts: NASA contract NAS7-918; DOE contract DEFG03-88er60683; NSF contracts DIR-8809710 and DMS-8815106; and NIH contract GM 36230, and is subject to the provisions of Public. Law 96-517 (35 USC 202) in which the Contractors have elected to retain title.
US Referenced Citations (5)
Non-Patent Literature Citations (8)
Entry |
"A Systolic Array for Rapid String Comparison" Lipton, 1985. |
"Identification of Common Molecular Subsequences." Waterman and Smith. |
"Bio Scan: A VLSI-Based System for Bio Sequence Analysis", White et al. 1991. |
The Design of Special-Purpose VLSI Chips Foster et al, 1980. |
"On High-Speed Compating with a Programmable Linear Array", Lee et al, 1988. |
"Why Systolic Architecture" Kung 1982. |
"The BioScan Project: An Interdisiplinary Approach to Biosequence Analysis" White et al, Oct. 1989. |
"A New Algorithm for Best Subsequence Alignment with Application to tRNA-rRNA Comparisons" Waterman et al. 1987. |
Continuations (2)
|
Number |
Date |
Country |
Parent |
154633 |
Nov 1993 |
|
Parent |
518562 |
May 1990 |
|