Patent Application
20130070410
1. Technical Field
The present disclosure relates to a serial advanced technology attachment dual in-line memory module (SATA DIMM) and a computer system having the SATA DIMM.
2. Description of Related Art
Solid state drives (SSD) store data on chips instead of magnetic or optical discs as traditional drives. One type of SSD has the form factor of a dual-in-line memory module (DIMM) module and is called a serial advanced technology attachment (SATA) DIMM. As such, the SATA DIMM can be inserted into a memory slot of a motherboard, to receive a voltage from the motherboard through the memory slot. However, hard disk drive (HDD) signals need to be transmitted between the SATA DIMM and the motherboard through a SATA connector set on the SATA DIMM connected to a SATA connector of the motherboard. Moreover, the SATA connector set on the SATA DIMM may occupy a lot of space. Therefore, there is room for improvement in the art.
Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
The disclosure, including the drawings, is illustrated by way of example and not by limitation. References to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.
Referring to
First and second storage device connectors 211 and 311 extend from two opposite ends 15 and 17 of the circuit board 10. The first storage device connector 211 includes a first extending board 20 extending from the end 15, and an edge connector 21 arranged on the first extending board 20. The second storage device connector 311 includes a second extending board 30 and an edge connector 31 arranged on the second extending board 30. The edge connectors 21 and 31 are connected to the control chip 11. The control chip 11 receives a control signal from the edge connector 21 and outputs the control signal through the edge connector 31, or receives a control signal from the edge connector 31 and outputs the control signal through the edge connector 21. The control chip 11 stores a control program for controlling the control signal received from the edge connector 21 and output through the edge connector 31 preferentially. Namely, the control chip 11 preferentially outputs the control signal received from the edge connector 21 through the edge connector 31. If the control chip 11 does not receive a control signal from the edge connector 21, the control chip 11 will output the control signal received from the edge connector 31 through the edge connector 21. Two grooves 16 are defined in each of the ends 15 and 17, and located under the first and second extending boards 20 and 30.
Each of the edge connectors 21 and 31 includes a pair of signal input pins, a pair of signal output pins, and three ground pins. The signal input pins and the signal output pins are connected to the control chip 11. The ground pins are connected to a ground layer (not shown) of the circuit board 10.
In one embodiment, the first and second storage device connectors 211 and 311 are in accordance with serial advanced technology attachment (SATA) standard.
Top surfaces 22 and 32 of the first and second extending boards 20 and 30 are lower than a top side 14 of the circuit board 10 opposite to the bottom side 18. When the first and second storage device connectors 211 and 311 are connected to storage device interfaces, top surfaces of the storage device interfaces are lower than or coplanar with the top side 14 of the board 10. Thus, reducing the interference between the SATA DIMM 100 and a chassis (not shown) when the SATA DIMM 100 is mounted on the motherboard 200 accommodated in the chassis.
In one embodiment, four memory slots 230, 240, 250, and 260 and two storage device interfaces 210 and 220 are arranged on the circuit board 201 of the motherboard 200. The storage device interfaces 210 and 220 are SATA connectors.
In assembly, first to fourth SATA DIMMs 100 are respectively inserted into the memory slots 230, 240, 250, and 260 through the edge connectors 19. The grooves 16 of the first to fourth SATA DIMMs 100 are respectively engaged with fixing elements 231, 241, 251, and 261 of the memory slots 230, 240, 250, and 260, to fix the first to fourth SATA DIMMs 100 on the motherboard 200.
The first storage device connector 211 of the first SATA DIMM 100 is connected to the storage device interface 210 through a cable 1 with two interfaces. The second storage device connector 311 of the first SATA DIMM 100 is connected to the first storage device connector 211 of the second SATA DIMM 100 through a cable 2 with two interfaces. The second storage device connector 311 of the second SATA DIMM 100 is connected to the first storage device connector 211 of the third SATA DIMM 100 through a cable 3 with two interfaces. The second storage device connector 311 of the third SATA DIMM 100 is connected to the first storage device connector 211 of the fourth SATA DIMM 100 through a cable 4 with two interfaces. The second storage device connector 311 of the fourth SATA DIMM 100 is connected to the storage device interface 220 through a cable 5 with two interfaces. Namely, the first to fourth SATA DIMMs 100 connected in series.
When the motherboard 200 receives power, the motherboard 200 outputs a voltage to the first to fourth SATA DIMMs 100 through the memory slots 230, 240, 250, and 260 and the edge connectors 19. At the same time, the motherboard 200 outputs a control signal to the control chip 11 of the first SATA DIMM 100 through the storage device interface 210, the cable 1, and the first storage device connector 211 of the first SATA DIMM 100. The control chip 11 of the first SATA DIMM 100 controls the storage chips 12 to store data and transmits the control signal to the control chip 11 of the second SATA DIMM 100 through the second storage device connector 311 of the first SATA DIMM 100, the cable 2, and the first storage device connector 211 of the second SATA DIMM 100. Similarly, the third SATA DIMM 100 receives the control signal from the second SATA DIMM 100, and the fourth SATA DIMM 100 receives the control signal from the third SATA DIMM 100, therefore, the first to fourth SATA DIMMs 100 can communicate with the motherboard 200.
Using the same theory, the motherboard 200 also outputs a control signal to the control chip 11 of the fourth SATA DIMM 100 through the storage device interface 220, the cable 5, and the second storage device connector 311 of the fourth SATA DIMM 100. The control chip 11 of the fourth SATA DIMM 100 controls the storage chips 12 to store data and transmits the control signal to the control chip 11 of the third SATA DIMM 100 through the first storage device connector 211 of the fourth SATA DIMM 100, the cable 4, and the second storage device connector 311 of the third SATA DIMM 100. Similarly, the second SATA DIMM 100 receives the control signal from the third SATA DIMM 100, and the first SATA DIMM 100 receives the control signal from the second SATA DIMM 100, therefore, the first to fourth SATA DIMMs 100 can communicate with the motherboard 200. Namely, when the first to fourth SATA DIMMs 100 of the memory slots 230, 240, 250, and 260 are normal, the first to fourth SATA DIMMs 100 of the memory slots 230, 240, 250, and 260 can receive a control signal from the motherboard 200 through the first storage device connector 211 of the first SATA DIMM 100 and the storage device interface 210, to communicate with the motherboard 200.
If the second SATA DIMM 100 is abnormal, the third and fourth SATA DIMM 100 cannot receive a control signal from the motherboard 200 through the first storage device connector 211 of the first SATA DIMM 100 and the storage device interface 210. Therefore, the control chips 11 of the third and fourth SATA DIMMs 100 need to receive a control signal from the motherboard 200 through the second storage device connector 311 of the fourth SATA DIMM 100 and the storage device interface 220, to communicate with the motherboard 200. When any one of the first to fourth SATA DIMMs 100 is abnormal, other SATA DIMMs 100 can continue working.
The first to fourth SATA DIMMs 100 of the memory slots 230, 240, 250, and 260 can be connected in series through the first and second storage device connectors 211 and 311, to communicate with the motherboard 200. Therefore, the motherboard 200 reduces the number of the storage device interfaces, which are arranged on the motherboard 200.
It is to be understood, however, that even though numerous characteristics and advantages of the disclosure have been set forth in the foregoing description, together with details of the structure and function of the disclosure, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and the arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 100133533 | Sep 2011 | TW | national |
