Serial data link using decision feedback equalization

Abstract

A multi-phase adaptive decision feedback equalizer minimizes post-cursor inter-symbol interference in a current data bit based on values of subsequent data bits in a data communication system. In one form, the receiver includes a plurality of modules each having a respective adaptive decision feedback equalizer. A processor responsive to output signals from each of the plurality of modules generates a plurality of coefficient values. The adaptive decision feedback equalizer has a plurality of taps receiving a respective output signal from one of the modules and a respective coefficient value to generate a respective correction signal. The correction signals are summed with the data signal and processed to recover the data. Pre-calculation of coefficients permits rapid selection of data. Multi-phase operation permits higher data frequencies.

Description

FIELD OF THE INVENTION

This invention is directed to data communications, and particularly to serial data links between a transmitting unit and a receiving unit.

BACKGROUND OF THE INVENTION

Reference is made to the article “A 4.8-6.4 Gbps Serial Link for Back-plane Applications using Decision Feedback Equalization” by the same inventors identified herein, published at Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, pages 31-34, October 2004, the content of which is hereby incorporated by reference in its entirety.

Copper traces on printed circuit boards (PCBs) are used as data channels to transmit digital data from a transmitting unit to a receiving unit on the PCB. These traces exhibit several loss mechanisms that degrade the data signal and generate inter-symbol interference (ISI) between data bits in a data string or bit stream. These loss mechanisms include skin effect, dielectric loss, and reflections from impedance discontinuities in the traces. These losses increase as data communication speeds increase. ISI increases with increased data speeds, resulting in increased bit error rates (BERs) and degradation of clock signals recovered from received data.

Advanced equalization techniques are employed to reduce ISI and recover data and clock from the data stream at the receiver. Some designs implement pre-emphasis to increase high-frequency gain of the transmitted signal to compensate for increased high-frequency losses though the channel. Other designs employ linear equalizers, such as finite impulse response (FIR) filters, to boost the high-frequency signals in the receiver. Yet other designs employ both transmitter pre-emphasis and receiver equalization. However, these techniques also boost high frequency noise and cross-talk, which can degrade performance. Moreover, cross-talk, which is already greater at higher frequencies, gets worse due to high frequency boost from the transmitter pre-emphasis and by the equalizer at the receiver.

An improved equalization technique is illustrated in FIG. 1, and employs a decision feedback equalizer (DFE) at the receiver that removes post-cursor ISI due to channel losses by feeding back decisions that are clean. As shown in FIG. 1, data transmitted by transmitter 10 are received from data channel 12 by receiver 14. Data, which may be distorted due to loss mechanisms in channel 12, are received by a forward equalizer 16. Forward equalizer 16 conditions the received signal by adjusting the signal gain so that the signal amplitude of data signals forwarded to summing device 18 is substantially constant. Data slicer 20 provides decisions to DFE 22 to supply a signal to summing device to cancel inter-symbol interference caused by the most recently processed bits from the presently received bit. An adaptive loop drives forward equalizer 16 and DFE 22 for optimal settings for given channel loss characteristics.

Data slicer 20 is timed by the clock recovered from the output data to provide clean decisions ±1 in the case of binary non-return to zero (NRZ) signaling. The decisions are fed back to DFE 22 to minimize ISI in subsequent bits. More particularly, the output from slicer 20 is applied to a voltage-controlled oscillator loop (not shown) to recover the clock signal in a well-known manner. The filter coefficients of forward equalizer 16 and DFE 22 are driven by the adaptation loop and set according to the most optimal settings for given channel loss characteristics that result in the lowest BER. In PCB applications, a target BER of 10⁻¹⁵ is typical.

The DFE system shown in FIG. 1 minimizes BER loss without boosting noise or cross-talk to achieve signal equalization. However, the system uses previous decisions to cancel ISI in the present bit. Consequently, the system is vulnerable to error-propagation.

The DFE system shown in FIG. 1 must be linear over the entire operating range of the circuit. Forward equalizer 16 requires considerable power to operate in a linear mode over a wide high frequency range. Thus, power limitations at the receiver end of channel 12 effectively eliminate implementation of the DFE system of FIG. 1 in PCBs and integrated circuit (IC) chips for wide high frequency ranges, such as at frequencies of 4.8 to 6.4 gigabits per second (Gbps). There is a need, therefore, for a data transmission system that is linear over a high frequency range and that does not require considerable power at the receiver.

SUMMARY OF THE INVENTION

In a first embodiment of the invention, a data communication apparatus is provided, such as on a printed circuit board or integrated circuit chip. The apparatus comprises a transmitter capable of transmitting data in the form of a data signal representing a string of binary data bits with at least two distinct amplitudes. A programmable feed-forward equalizer minimizes pre-cursor inter-symbol interference in the data signal. A data channel transmits the data signal to a receiver that receives the data signal. A multi-phase adaptive decision feedback equalizer at the receiver minimizes post-cursor inter-symbol interference in a current data bit of the received data signal based on values of subsequent data bits.

In preferred embodiments, the receiver comprises a plurality of modules, each providing an output during a respective clock phase. An adaptive decision feedback equalizer in each module modifies the data signal received from the channel based on the output signals of the plurality of modules.

In some embodiments, each adaptive decision feedback equalizer has a plurality of taps responsive to respective module output signals and a respective coefficient value to generate respective correction signals, and a summing device modifies the data signal based on the plurality of correction signals. The number of taps in each adaptive decision feedback equalizer is based on a number of bits causing post-cursive inter-symbol interference in a data bit in the string.

Optionally, the taps are arranged in pairs using pre-calculated coefficients with a selection of the modified data signal performed on the basis of a subsequent bit value.

Another embodiment of the invention is directed to a process of transmitting data over a data channel between a transmitting circuit and a utilization circuit wherein a decision feedback equalizer is adapted to minimize post-cursor inter-symbol interference in a bit in the received data signal based on a bit value of a subsequent bit in the received data signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of data transmission system employing a conventional adaptive decision feedback equalizer.

FIG. 2 is a graph demonstrating the effects of a pre-emphasis filter according to the present invention.

FIG. 3 is a block diagram of data transmission system employing an adaptive decision feedback equalizer according to an embodiment of the present invention.

FIG. 4 is a functional diagram of an embodiment of a transmitter forward filter shown in FIG. 3.

FIG. 5 is a block diagram of a pre-emphasis filter according to an embodiment of the present invention.

FIG. 6 is a functional diagram of the pre-emphasis filter shown in FIG. 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 illustrates a typical pulse response for transmission of a binary ‘1’, preceded and followed by long series of 0's. The data points on the graph are spaced one bit period apart and represent sampling points. Curve 30 denotes the pulse response without pre-cursor feed forward equalization. Peak 32 demarcates the sampling position for the single ‘1’. Data points 34 that precede peak 32 with non-zero magnitude represent pre-cursor inter-symbol interference that will interfere with previously transmitted bits. Data points 36 that follow peak 32 with non-zero magnitude represent post-cursor ISI and represent noise to subsequently transmitted bits. The goal of the present invention is to remove as much ISI as possible while minimizing cross talk enhancement. This is accomplished by use of a programmable feed forward equalization filter 24 and an adaptive decision feedback equalizer 22 shown in FIG. 3.

In a first embodiment of the invention, shown in FIG. 3, the function of forward emphasis filter 16 of the prior art system is moved to the transmitter side of channel 12. This is possible because both channel 12 and the filter are linear systems and their order can be swapped. However, since the adaptive loop is not available to the filter in the transmitter side, a programmable forward de-emphasis filter 24 is substituted for the adaptive forward equalizer filter of the prior art system. As a de-emphasis filter, filter 24 operates on known data and is easier to design. It also ensures backward compatibility with legacy systems at half-rate or quarter-rate modes. Thus, the embodiment shown in FIG. 3 employs a programmable forward de-emphasis filter 24 at the transmitter side of channel 12, and a fully adaptive decision feedback equalizer 22 at the receiver side of channel 12.

In preferred embodiments, feed forward equalizer 24 is a finite impulse response (FIR) filter having some number of taps. The number of taps on equalizer 24 is empirically selected based on the number of significant pre-cursor ISI samples in the pulse response. The pulse response in FIG. 2 shows only one significant sample 34 of pre-cursor ISI, implying that a two-tap FIR filter would be adequate for the feed-forward equalizer.

FIG. 4 illustrates the transfer function of a two tap FIR transmit filter 24. For input a_k, and delay D, the transfer function is −α+D and the output is b_k=−αa_k+a_k−1. Application of filter 24 adjusts the pulse response to curve 38 in FIG. 2.

Data slicer 20 in FIG. 3 makes decisions each bit period, T, during which the decision feedback equalizer filter 22 processes the information to cancel ISI from the present incoming symbol. In order to cancel ISI from the present bit based on the most recent bit, the following timing constraint must be observed: T_ck-Q+T_delay—DFE+T_setup≦T  (1) where, T_ck-Q is the clock-to-data delay of the slicer, T_delay—DFE is the delay of filter 22, and T_setup is the setup time of the slicer. In 0.13 μm CMOS technology and for operation at 6.4 Gbps (gigabits per second), T=156.25 ps (picoseconds. This timing constraint may be eased by storing results of a pre-calculation of every possible combination of the previous bit (in parallel) to cancel ISI and then making a choice once the data are known. The stored pre-calculation results ease the requirement for high power at the receiver in some applications.

In the present invention, it is desired to perform as much of the equalization as possible at the receiver end of channel 12. Decision feedback equalizer 22 is adaptive and does not enhance high frequency cross talk. Decision feedback equalizer 22 is capable of removing post-cursor ISI, but not the pre-cursor ISI. Consequently, feed forward equalizer 24 at the transmitter end of channel 22 is used to mitigate the pre-cursor ISI.

In preferred embodiments, the receiver employs a multi-phase clocking scheme. In one embodiment, shown in FIG. 5, a four-phase design employs four modules 40, 42, 44 and 46 each operating to provide an output D0, . . . , D3 during a respective phase (φ_i, i=3, . . . , 0). Each phase provides a pulse whose duty cycle is 4T in duration. Pulse transitions are offset by T from two other clock phases. This four-phase design allows a lower frequency (¼ f) for each phase and permits use of a low power/area ring voltage-controlled oscillator 48 to generate the clock pulses for phases φ₃, . . . , φ₀. Thus, for a 6.4 GHz clock rate, each phase operates at 1.6 GHz. This design makes is easier to distribute the clock on-chip. Baud-rate sampling is used to capture the data as well as generate error signals for driving the timing, gain and coefficient adaptation loops. The equalized data eye is sampled in the center with a 2-bit analog-to-digital converter to generate an error signal, E, and data signal, D.

In the prior art decision feedback filter system shown in FIG. 1, the adaptive forward equalizer filter 16 controls the gain of the incoming signal such that the amplitude seen by the analog-to-digital converter is constant, that is, filter 16 provides automatic gain control. In the present invention, since the function of filter 16 is at the transmitter in the form of filter 24, a “gain loop” is employed at the receiver to adjust the size of the least significant bit in the data slicer, which in FIG. 5 is a two-bit data slicer.

As the incoming amplitude changes from one channel to another or as a result of transmitter broadcast amplitude settings, the target amplitude, h₀, internal to the receiver changes until it reaches steady state. A large incoming amplitude will cause a higher h₀, and vice-versa. This can be represented by the following equation: Vin_k−Σh_n·{circumflex over (D)}_i=±h₀,  (2) where Vin_k is the k^th sample of Vin, h_n are filter coefficients for the decision feedback equalizer, {circumflex over (D)}_k-n is the detected data and h₀ is the target amplitude target, which is the same as the threshold for the data slicer. A coefficient adaptation loop adjusts h_n and a gain loop adjusts h₀. In the embodiment of FIG. 5, the coefficient adaptation loop and gain loop operate together to satisfy equation (2) for every sample.

The coefficient feedback loop employs a plurality of feedback equalization taps, the number of which is based on an analysis of the pulse response. Conveniently, the number of phases of the multi-phase clock is equal to the number of taps of the coefficient adaptation loop. As is seen in the pulse response of FIG. 2, post-cursor ISI trails off more slowly compared to pre-cursor ISI.

We have found that four taps provide adequate performance. While performance continues to improve as the number of feedback taps increases, any additional taps provide only marginal benefit and do not justify the additional cost in complexity and power to the circuit. Consequently, the 4-tap, 4-phase feedback equalizer shown in FIG. 5 is preferred.

As shown in FIG. 5, and particularly in module 40, each of the four taps in each module 40, . . . , 46 comprises a pair of multipliers comprising one multiplier 52 and one multiplier 54. In each module, one tap is formed by a multiplier 52 receiving a value of +1 and a multiplier 54 receiving a value of −1. The value ±1 represents the value of the next bit, which in the case of module 40 is D0. The other three taps receive the bit values of the next three bits, which in the case of module 40 are ±D1, ±D2 and ±D3, respectively. Thus, multipliers 52 receive +1, +D1, +D2 and +D3, whereas multipliers 54 receive −1, −D1, −D2 and −D3. The multiplier pairs representing each tap multiply the values of the respective signals by a coefficient h₁, h₂, h₃ and h₄, respectively.

FIG. 6 is a functional diagram of one of the sets of multipliers 52 or 54, such as multipliers 52 of module 40 in FIG. 5. The other set of multipliers is similar. The input signal {circumflex over (α)}_k is the succession of signals D0, . . . , D3 which are delayed from each other by a delay D, representing bit period T. Each signal D0, . . . , D3 is applied a respective multiplier 52a, . . . , 52d, which in turn multiplies the signal by a coefficient h₁, . . . , h₄. The result is summed to provide a signal, z_k. For four taps, the output of the feedback equalizer will be $\begin{array}{cc}{z}_k=\sum _{j=1}^4{h}_{j,k},{\hat{D}}_{k-j}& \left(3\right)\end{array}$ where, {circumflex over (D)}_k is the detected data bit at time k and h_j,k is the value of the j^th tap of the feedback equalizer at time k. The output of the feedback equalizer is subtracted from the received signal sample, Vin_k, the input to the slicer is: $\begin{array}{cc}{y}_k={\mathrm{Vin}}_k-z_k={\mathrm{Vin}}_k-\sum _{j=1}^4{h}_{j,k},{\hat{D}}_{k-j}.& \left(4\right)\end{array}$

Multipliers 52 and 54 provide pre-calculation of coefficients. The value of a coefficient may be either positive or negative, depending on the value of the data bits. The value ±1 is applied for the next bit (D0 in module 40). Multiplier 52a multiplies +1 by coefficient h₁ (corresponding multiplier 54a multiplies −1 by coefficient h₁). In this manner, the tap outputs ±1·h₁ to the respective summing devices 55. Similarly, multipliers 52b and 54b forming the next tap output ±D1h₂ (module 40) to summing devices 55, and so on. Multipliers 52 collectively calculate the value of +z_k that is subtracted from the input Vin_k. Multipliers 54 collectively calculate the value of −z_k that is subtracted from Vin_k.

The equalizer taps are set adaptively by processor 50 which receives the data and error outputs D0, . . . , D3 and E0, . . . , E3. The error signal E that drives this loop is the sign of the difference between the input and the output of the slicer, E_k=sign({circumflex over (D)}_kh_0,k−y), where h_0,k is the ideal value of the received sample estimated at time k. The feedback equalizer taps use the error signal in a sign-sign least mean squares (LMS) algorithm to adapt the equalizer taps each 4T time period as: h_j,k=h_j,k-4−μ_hΔh_j,k,  (5) where $\Delta h_{j,k}=\mathrm{sign}\left(\sum _{i=1}^4\mathrm{sign}\left(E_{k-i}·{\hat{D}}_{k-i-j}\right)\right)$ and μ_h is a scale factor that determines the bandwidth of the feedback tap adaptation.

The error signal depends on the comparison of the received signal with the ideal signal level, which can vary depending on the voltage swing of the transmitted signal as well as the quality of the channel. The level of the ideal signal level is adapted automatically each 4T as h_0,k=h_0,k-4−μ_γΔh_0,k,  (6) where $\Delta h_{0,k}=\mathrm{sign}\left(\sum _{i=1}^4\mathrm{sign}\left(E_{k-i}·{\hat{D}}_{k-i}\right)\right)$ and μ_γ is a scale factor that controls the bandwidth of the ideal signal level adaptation.

Processor 50 in FIG. 5 receives the error and data signals from modules 40, . . . , 46 to calculate the values of h₁, h₂, h₃, h₄ from equation (5) and the value of h₀ from equation (6). The values of h₁, . . . , h₄ are applied to multipliers 52 and 54 for the “coefficient adaptation” loop and the value of h₀ is applied to data slicers 56 for the “gain” loop.

The two values of the summed input, y_k, are applied to respective data slicers 56, 58 and 60. The data slicers are arranged in pairs, with one slicer 56, 58, 60 of each pair being connected to the input summed with multipliers 52 and the other slicer 56, 58, 60 of each pair being connected to the input summed with multipliers 54. The pair of slicers 56 operate with a target value of +h₀, the pair of slicers 58 operate with a target value of 0 and the pair of slicers 60 operate with a target value of −h₀. The pairs of slicers 56, 58, 60 are coupled to respective selectors 62 which are operated by output of the prior data bit, D0 in the case of module 40, to select one of the pre-calculated sets of coefficients to output the selected data slices to an analog-to-digital converter formed of respective flip-flops 64 and decoder 66. Decoder 66 provides data and error signal outputs, which are used to adaptively adjust coefficients h₀, . . . , h₄ and generate the phase definitions φ₃, . . . , φ₀.

The φ₃, . . . , φ₀ phase signals generated by oscillator 48 drive data slicers 56, 58, 60 and flip-flops 64 in each module. Selectors 62 are timed by the data signal from the next module. Considering module 40 in FIG. 5, data slicers 56, 58 and 60 are enabled during the φ₃ phase to provide outputs to selectors 62 based on ±z_k and ±h₀ or 0. Selectors 62 are enabled by the D0 data signal, which was generated during the same φ₃ phase. Hence, selectors 62 select three values from the six data slicers based on either +z_k or −z_k and ±h₀ or 0. The selection is based on the value of D0. The selected values operate respective flip-flops 64 and are decoded by decoder 66 to supply D3 data and E3 error signals to oscillator 48 and processor 50 and to supply data D3 to the user circuit.

At phase φ₂, which is immediately before the next phase φ₃, flip-flops 64 are reset in readiness for the next cycle. Modules 42, 44 and 46 are operated in the same manner with the data slicers being operated during phase φ₂ and flip-flops reset during phase φ₁ (module 42), during phases φ₁ and φ₀ (module 44) and during phases φ₀ and φ₃ (module 46).

Thus, the output of each flip-flop 64 is the output of a selected data slicer 56, 5860. The flip-flops latch and hold the output for a period of 4T, with each decoder 66 supplying the output to the other modules. Thus the D3 output feeding into the respective taps 52, 54 of module 40 is actually the D3 output from 4T ago and is used to cancel ISI from the present bit. Similarly, the D2 output from module 42 feeding into taps of module 40 is the D2 output from 2T ago.

Phase update is driven by baud rate spaced samples. To accommodate large frequency offsets without severely impacting jitter tolerance performance, a second order timing loop is employed in oscillator 48 to generate a phase update term Δt_k=sign(Σsign(E_k-1·{circumflex over (D)}_k-1-i−e_k-1-i·{circumflex over (D)}_k-i))  (7) The sampling position is updated each 4T as t_k=t_k-4−μ_tΔt_k−Δf_k, where Δf_k=Δf_k-4−μ_fΔt_k is the frequency term, μ_γ controls the bandwidth of the phase update, and μ_f determines the bandwidth of the frequency-offset update.

In preferred embodiments, the number of possible phases per bit time that could be selected by the timing loop is 64 for the 4T system. In most conditions, jitter will cause the timing loop to dither between two or three sampling positions. With a resolution of 16 sampling positions per bit time, signal-to-noise degradation is minimized.

Because the feedback equalizer taps h₁, . . . , h₄ and ideal signal level h₀ are determined adaptively, an initialization sequence is required. While there is no requirement for any particular data pattern to be used for initialization, the sequence that is used must be spectrally rich such as a pseudo-random bit sequence. During initialization, the timing and signal level loops are activated first with the feedback equalization loop frozen. The feedback equalizer adaptation loop is then enabled and all of the loops are allowed to settle. The entire process will be completed within a maximum of few hundred thousand bit times depending on the loop bandwidth settings.

The present invention thus provides a robust adaptive decision feedback equalizer that is capable of operating at high frequencies, such as in the range of 4.8 to 6.4 Gbps. By sampling bits in parallel modules at lower speeds, post-cursive ISI can be minimized based on actual subsequent bits. Thus, each module can view later bit values and minimize post-cursive ISI in a present bit. This offers significant advantage over prior systems that interpreted post-cursive ISI on the basis of prior bits, rather than subsequent bits.

Pre-calculation of filter coefficients permits rapid generation of a plurality of correction signals and generation of plural data slices with selection of data values being made based on the subsequent bit. Consequently, the system operates well at high frequencies.

While the invention is described employing the same number of taps in the decision feedback equalizers as there are phases of the clock, the number of clock phases and modules may be greater than the number of taps, in which case the taps of each module receive less than all of the outputs of the next modules.

Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.

Claims

1. Data communication apparatus comprising: a transmitter capable of transmitting data in the form of a data signal representing a string of binary data bits, the data signal having at least two distinct amplitudes, the transmitter having a programmable feed-forward equalizer for minimizing pre-cursor inter-symbol interference in the data signal; a data channel coupled to the transmitter to transmit the data signal; and a receiver coupled to the data channel to receive the data signal, the receiver having a multi-phase adaptive decision feedback equalizer for minimizing post-cursor inter-symbol interference in a current data bit based on values of subsequent data bits.

2. The apparatus of claim 1, wherein the feed-forward equalizer is a finite impulse response filter having a plurality of taps based on a number of bits causing pre-cursor inter-symbol interference in a data bit in the string.

3. The apparatus of claim 1, wherein the receiver further comprises a plurality of modules coupled to the data channel, each module comprising: a respective adaptive decision feedback equalizer responsive to an output signal from a plurality of modules that includes at least one other module to modify the data signal based on the output signals of the plurality of modules.

4. The apparatus of claim 3, wherein the receiver further comprises: a processor responsive to output signals from each of the plurality of modules to generate a plurality of coefficient values, and each adaptive decision feedback equalizer further comprises: a plurality of taps each responsive to a respective output signal from one of the modules and a respective filter coefficient value to generate a respective correction signal, and a summing device for summing the plurality of correction signals and the data signal.

5. The apparatus of claim 4, wherein the number of taps is based on a number of bits causing post-cursor inter-symbol interference in a data bit in the string.

6. The apparatus of claim 4, wherein each module further comprises: a data slicer responsive to the modified data signal and a target value to sample a value of a bit, and an analog-to-digital converter responsive to the sampled bit values to provide the output signal from the module.

7. The apparatus of claim 6, wherein the plurality of taps are arranged in pairs to generate respective first and second correction signals based on a respective filter coefficient and the output signal from a respective module, and wherein the summing device comprises a first summing device providing a first modified data signal based on the received data signal and the first correction signal and a second summing device providing a second modified data signal based on the received data signal and the second correction signal, the data slicer further comprises: a plurality of pairs of data slicers, each pair being responsive to a respective target value to sample the respective first and second modified data signals, a selector responsive to an output from another module for selecting samples of one of the first and second modified data signals.

8. The apparatus of claim 6, further comprising: a multi-phase clock responsive to the output signals from each of the plurality of modules to generate a plurality of clock signals having different phases, the data slicers of each module being responsive to a clock signal having first phase to sample a bit value and the analog-to-digital converter being responsive to a clock signal having a second phase, different from the first phase, to clear the sampled value from the converter, the first phase for each module being different from the first phase for each other module.

9. The apparatus of claim 3, wherein each module further comprises: a data slicer responsive to the modified data signal and a target value to sample a value of a bit, and an analog-to-digital converter responsive to the sampled bit values to provide the output signal from the module.

10. The apparatus of claim 9, further comprising: a multi-phase clock responsive to the output signals from each of the plurality of modules to generate a plurality of clock signals having different phases, the data slicers of each module being responsive to a clock signal having first phase to sample a bit value and the analog-to-digital converter being responsive to a clock signal having a second phase, different from the first phase, to clear the sampled value from the converter, the first phase for each module being different from the first phase for each other module.

11. The apparatus of claim 3, further comprising: a processor responsive to output signals from each module for calculating filter coefficients, each adaptive decision feedback equalizer being responsive to output signals from a plurality of modules and the calculated filter coefficients to modify the received data signal to provide first and second modified data signals, and a selector responsive to the first and second modified data signals and the output signal from a different module to select one of the first and second modified data signals.

12. A printed circuit board or integrated circuit chip data containing: a first circuit capable of transmitting data in the form of a data signal representing a string of binary data bits, the data signal having at least two distinct amplitudes; a programmable feed-forward equalizer coupled to the first circuit to minimize pre-cursor inter-symbol interference in the data signal; a data channel coupled to the feed-forward equalizer to transmit the data signal; a utilization circuit coupled to the data channel to receive the data signal; and a multi-phase adaptive decision feedback equalizer in the utilization circuit and to minimize post-cursor inter-symbol interference in a current data bit of the received data signal based on values of subsequent data bits.

13. The apparatus of claim 12, wherein the utilization circuit comprises a plurality of modules coupled to the data channel, a respective adaptive decision feedback equalizer in each module being responsive to an output signal from a plurality of modules that includes at least one other module, each decision feedback equalizer modifying the data signal based on the output signals of the plurality of modules.

14. The apparatus of claim 12, wherein the utilization circuit further comprises: a processor responsive to output signals from each of the plurality of modules to generate a plurality of coefficient values, and each adaptive decision feedback equalizer further comprises: a plurality of taps each responsive to a respective output signal from one of the modules and a respective filter coefficient value to generate a respective correction signal, and a summing device for summing the plurality of correction signals and the data signal.

15. The apparatus of claim 13, wherein each module further comprises: a data slicer responsive to the modified data signal and a target value to sample a value of a bit, and an analog-to-digital converter responsive to the sampled bit values to provide the output signal from the module.

16. The apparatus of claim 15, wherein the plurality of taps are arranged in pairs to generate respective first and second correction signals based on a respective filter coefficient and the output signal from a respective module, and wherein the summing device comprises a first summing device providing a first modified data signal based on the received data signal and the first correction signal and a second summing device providing a second modified data signal based on the received data signal and the second correction signal, the data slicer further comprises: a plurality of pairs of data slicers, each pair being responsive to a respective target value to sample the respective first and second modified data signals, a selector responsive to an output from another module for selecting samples of bit values from respective ones of the pairs of data slicers.

17. The apparatus of claim 15, further comprising: a multi-phase clock responsive to the output signals from each of the plurality of modules to generate a plurality of clock signals having different phases, the data slicers of each module being responsive to a clock signal having first phase to sample a bit value and the analog-to-digital converter being responsive to a clock signal having a second phase, different from the first phase, to clear the sampled value from the converter, the first phase for each module being different from the first phase for each other module.

18. A process of transmitting data in a printed circuit board or integrated circuit having a data transmitting circuit, a utilization circuit and a data channel coupling the transmitting and utilization circuits, wherein the data are in the form of a data signal representing a string of binary data bits, the data signal having at least two distinct amplitudes, the process comprising steps of: a) minimizing pre-cursor inter-symbol interference in the data signal at the transmitting circuit; b) transmitting the data signal with minimized pre-cursor inter-symbol interference to the utilization circuit via the data channel; c) receiving the transmitted data signal at the utilization circuit; and d) adapting a decision feedback equalizer to minimize post-cursor inter-symbol interference in a bit in the received data signal based on a bit value of a subsequent bit in the received data signal.

19. The process of claim 18, wherein step d) comprises steps of: d1) pre-calculating coefficient values based on assumed bit values, d2) operating the decision feedback equalizer using the pre-calculated coefficient values to generate plural versions of a modified data signal, and d3) selecting one of the modified received data signals to minimize post-cursor inter-symbol interference in a bit in the received data signal based on a bit value of a subsequent bit in the received data signal.

20. The process of claim 18, wherein step (d) comprises steps of: d1) sampling an amplitude of the received data signal during a first bit period, d2) generating a signal representing post-cursor inter-symbol interference during a second bit period subsequent to the first bit period, and d3) modifying the received data signal based on the signal representing post-cursor inter-symbol interference.