Wired communication refers to the transmission of data over a wire-based communication technology. Receiving such data, particularly at high data rates, requires sensitive, linear analog amplifiers. An amplifier is linear if its output is a linear function of its input, which means in part that signal components of different frequencies receive the same level of amplification. Linearity is difficult to obtain in practice and is a main factor limiting the speed performance of analog receivers.
The detailed description is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
A set of sixteen time-interleaved analog samplers 110[16:1] samples equalized continuous-time signal Deq using sixteen differently phased clock signals Clk1 through Clk16 to obtain sixteen respective series of analog samples Da1 through Da16. Timing circuitry 112 derives clock signals Clk1 through Clk16 from a reference clock signal Clk synchronized to signal Data. Each analog sample expressed in series Da1 through Da16 is a voltage level corresponding to one symbol time of equalized continuous-time signal Deq. Time interleaving samplers 110[16:1] reduces the sample rate by a factor of sixteen, and thus relaxes time constraints on downstream circuitry and increases overall gain bandwidth. In this embodiment in which signal Data is conveyed at 56 GBd, for example, analog sample streams Da1 through Da16 are each conveyed at about 3.5 GBd. The number of time-interleaved analog samplers can be generalized to N, which may be more or fewer than sixteen in other embodiments. Analog samplers, such as so-called “track-and-hold amplifiers,” are well known to those of skill in the art.
Each of the sixteen time-interleaved analog samplers 110[16:1] feeds a corresponding one of sixteen discrete-time variable-gain amplifiers 115[16:1]. Amplification through discrete-time variable-gain amplifiers 115[16:1] is linear relative to continuous-time variable-gain amplifiers and contributes to the overall linearity of receiver 100. Considering equalized, continuous-time signal Da1, for example, one of discrete-time variable-gain amplifiers 115[16:1] provides linear amplification of that series of analog symbols to produce an amplified series of analog samples Da1(k). Timing circuitry 112 controls the timing of discrete-time variable-gain amplifiers 115[16:1] by issuing sixteen sets of reset and evaluation signals Rst #/Eval #, examples of which are detailed below in connection with
Signals Rst1 and Eval1, both digital, are low from time T0 to T1 to open switching elements 210 and 210. Output nodes Da1(k) thus float at voltages that are a function of a prior symbol. Reset signal Rst1 is asserted at time T1 to close switching elements 220 to discharge capacitors 215. Both nodes Da1(k) are thus set to the high supply voltage Vdd and their differential value to zero. An evaluation stage begins at time T2 when reset signal Rst1 returns low and evaluation signal Eval1 is asserted. Switching elements 220 open and switching elements 210 close. The relative voltages across capacitors 220 thus change as a function of the currents through transistors M1 and M2, and thus the differential voltage across the gates of transistors M1 and M2. The voltage across each capacitor 215, and thus across output nodes Da1(k), changes linearly responsive to the constant currents pulled by current sources 200. Beginning evaluation with output nodes Da1(k) at supply voltage Vdd maximizes signal headroom and amplitude to further contribute to linearity. Source degeneration established by resistor 205 also contributes by reducing the impact of the input transconductances of transistors M1 and M2 on the gain of amplifier 115(1). Resistance 205 can be tuned to establish a desired level of source degeneration and to match and calibrate amplifier 115(1) with respect to the other variable-gain amplifiers 115[16:2].
The evaluation stage ends at time T3 when evaluation signal Eval1 is deserted, leaving a measure of symbol magnitude stored as a voltage across nodes Da1(k). Quantizer 120(1) quantizes the analog value of signal Da1(k) between times T3 and T4 to produce a digital value D1(k) (
Input signal Data is a PAM-4 signal (for pulse-amplitude modulation, 4-level) in the example of
In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding. In some instances, the terminology and symbols may imply specific details that are not required. The term “coupled,” for example, is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Furthermore, while the subject matter has been described in connection with specific embodiments, other embodiments are also envisioned. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. § 112.
Filing Document | Filing Date | Country | Kind |
---|---|---|---|
PCT/US2019/023913 | 3/25/2019 | WO | 00 |
Number | Date | Country | |
---|---|---|---|
62727365 | Sep 2018 | US | |
62659456 | Apr 2018 | US |