Serial Peripheral Interface for a Transceiver Integrated Circuit

A portion of the disclosure of this patent document may contain material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. The following notice shall apply to this document: Copyright© 2008 Microsoft Corp.

FIELD OF TECHNOLOGY

The presently disclosed subject matter relates to the field of computing and electronics, and more particularly, to fields such as entertainment consoles, although these are merely exemplary and non-limiting fields.

BACKGROUND

Video game and entertainment systems are increasingly incorporating new features and accessories. Development of accessories, such as wireless radios, and the necessary drivers require significant design effort. In turn, the commands and protocols required to control and manage the interfaces can be complicated and require significant development resources for developers of software and hardware accessories. Furthermore, technologies and related standards change on a frequent basis, requiring developers to adapt to new interface requirements. Thus a developer's investment in developing products for a particular interface may not be recouped when the interfaces and protocols frequently change.

Nevertheless, it would be advantageous to use an existing standard interface developing features and accessories. An interface standard widely used in the industry and supported by a large number of products typically drive down costs, and incorporation of such off the shelf components is desirable to reduce the cost of product development. Furthermore, in the case of a wireless transceiver, it is typically desirable to limit the number of integrated circuit (IC) pins needed to support inter-processor communications, while at the same time providing sufficient data bandwidth. Therefore, a simple serial interface may be selected for a wireless architecture. One such standard interface commonly used and well known in the art that provides such features is the Serial Peripheral Interface (SPI). One limitation of the SPI interfaces is that data transfers are limited to 8 bits at one time. Because many applications may require higher command and data transfer capability, a higher level protocol is needed that has the advantages of a serial interface.

In an SPI link there are typically four different operational modes possible. Both ends of the interface must agree to one before starting communications. This can be accomplished by many methods but they require extra IC pins to be used. Another possibility is to only support one mode and require the Master end to support the selected one. This limits flexibility within the platform. It would be advantageous for devices in an SPI link to be able to select an operational mode without the need for additional pins

Another problem with the SPI interface relates to the need of a Chip Select signal. This is normally used if the bus is shared between multiple slave devices. In an application in which only one slave device is implemented, the Chip Select signal is not required and can be tied to an always active state. This now presents a problem with byte framing on the bus. Each transfer is defined as the movement of one byte of data. If, for some reason a clock edge is missed or an extra created and no method exists to define the correct end of the byte transfer, the Master and Slave would become un-synchronized and self-recovery would not be possible. A method which permits frame timing on the SPI bus to be restored without resetting the slave device would be desirable.

SUMMARY

Various systems, methods, and computer readable media are disclosed herein for providing a platform to support the development of new accessories for video game and entertainment systems using serial interfaces such as the Serial Peripheral Interface (SPI). In one exemplary and non-limiting aspect of the present disclosure, a smart transceiver device may contain the complete physical (PHY) and media access control (MAC) layers of a wireless protocol stack, and the wireless protocol functionality may be partitioned into a single device.

In various embodiments, a protocol is disclosed that may be used to provide control and data transfer to and from such a smart transceiver device. In particular, an exemplary format for the protocol, the commands, and responses is disclosed. Such an exemplary format may be suitable for use in both wired and wireless implementations.

In a further embodiment, a method for mode synchronization that does not require the use of additional pins and can be accomplished with the standard SPI pins is disclosed. In an embodiment, the method used to select the correct mode used by the slave occurs immediately after a slave reset. The slave may start up in a “Mode Detect” state. The SPI port may then wait for a Mode byte to be sent to it from the Master. The Mode byte is sent in the correct mode the Master wishes to use. The slave measures the Mode byte to determine which of the four modes was used to send it. The Mode byte may be detected three times to ensure proper detection. This byte is repeatedly transmitted until the slave responses to these bytes by returning a 0x00 byte. When the Master receives this reply, the Mode Detect phase of the SPI bus has been completed. The slave will now be in the correct SPI operating mode.

In another embodiment, a method that permits frame timing on the SPI bus to be restored without resetting the slave device is disclosed. The SPI Frame Resynchronization procedure may be invoked by the master detecting the messages being received from the slave are not valid. This can be done in at least three ways:

An undefined command was received

A command was sent but no response was received

The Frame length field was not valid

In other embodiments the slave device may detect errors using similar approaches, i.e. illegal command and length not valid. If these conditions occur, the master device may reset the interface.

When the Frame error has been detected, the master repeatedly sends an SPI reset command (0xFF) until it receives an acknowledgement from the slave. The Acknowledgement is data is 0xFF with the Data Available interrupt line active. This indicates that the slave has data to send but is only sending an invalid command (the 0xFF command byte is reserved during normal use). By this method, the master now knows the slave SPI port is back into the Mode Detect state and it must re-initialize the SPI port.

It should be noted that this Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing Summary, as well as the following Detailed Description, is better understood when read in conjunction with the appended drawings. In order to illustrate the present disclosure, various aspects of the disclosure are illustrated. However, the disclosure is not limited to the specific aspects shown. The following figures are included:

FIG. 1 illustrates an exemplary console for subject matter discussed herein;

FIG. 2 illustrates an exemplary computing environment for subject matter discussed herein;

FIG. 3 illustrates an exemplary networking environment for subject matter discussed herein;

FIG. 4 illustrates an exemplary data transfer using an embodiment of a protocol disclosed herein;

FIG. 5 illustrates an exemplary method of selecting an operational mode using an embodiment disclosed herein;

FIG. 6 illustrates an example of a frame resynchronization sequence disclosed herein;

FIG. 7 illustrates an exemplary method of frame resynchronization disclosed herein;

FIG. 7
a illustrates an exemplary system for frame resynchronization disclosed herein;

FIG. 8 illustrates a typical data transfer using a protocol disclosed herein;

FIG. 9 illustrates an exemplary timing diagram depicting bus transfers using an embodiment of a protocol disclosed herein;

FIG. 10 illustrates an exemplary timing diagram depicting bus transfers using an embodiment of a protocol disclosed herein;

FIG. 11 illustrates an exemplary timing diagram depicting bus transfers using an embodiment of a protocol disclosed herein;

FIG. 12 illustrates an exemplary timing diagram depicting bus transfers using an embodiment of a protocol disclosed herein;

FIG. 13 illustrates an exemplary timing diagram depicting bus transfers using an embodiment of a protocol disclosed herein;

FIG. 14 illustrates an exemplary timing diagram depicting bus transfers using an embodiment of a protocol disclosed herein; and

FIG. 15 illustrates an exemplary timing diagram depicting bus transfers using an embodiment of a protocol disclosed herein.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Exemplary Game Console, PC, and Networking Aspects

This section of the present disclosure provides the general aspects of an exemplary and non-limiting game console. Referring now to FIG. 1, a block diagram shows an exemplary multimedia console. The multimedia console 100 has a central processing unit (CPU) 101 having a level 1 (L1) cache 102, a level 2 (L2) cache 104, and a flash ROM (Read-only Memory) 106. The level 1 cache 102 and level 2 cache 104 temporarily store data and hence reduce the number of memory access cycles, thereby improving processing speed and throughput. The flash ROM 106 may store executable code that is loaded during an initial phase of a boot process when the multimedia console 100 is powered. Alternatively, the executable code that is loaded during the initial boot phase may be stored in a flash memory device (not shown). Furthermore, ROM 106 may be located separate from CPU 101.

A graphics processing unit (GPU) 108 and a video encoder/video codec (coder/decoder) 114 form a video processing pipeline for high speed and high resolution graphics processing. Data is carried from the graphics processing unit 108 to the video encoder/video codec 114 via a bus. The video processing pipeline outputs data to an A/V (audio/video) port 140 for transmission to a television or other display. A memory controller 110 is connected to the GPU 108 and CPU 101 to facilitate processor access to various types of memory 112, such as, but not limited to, a RAM (Random Access Memory).

The multimedia console 100 includes an I/O controller 120, a system management controller 122, an audio processing unit 123, a network interface controller 124, a first USB host controller 126, a second USB controller 128 and a front panel I/O subassembly 130 that are preferably implemented on a module 118. The USB controllers 126 and 128 serve as hosts for peripheral controllers 142(1)-142(2), a wireless adapter 148, and an external memory unit 146 (e.g., flash memory, external CD/DVD ROM drive, removable media, etc.). The network interface 124 and/or wireless adapter 148 provide access to a network (e.g., the Internet, home network, etc.) and may be any of a wide variety of various wired or wireless interface components including an Ethernet card, a modem, a Bluetooth module, a cable modem, and the like.

System memory 143 is provided to store application data that is loaded during the boot process. A media drive 144 is provided and may comprise a DVD/CD drive, hard drive, or other removable media drive, etc. The media drive 144 may be internal or external to the multimedia console 100. Application data may be accessed via the media drive 144 for execution, playback, etc. by the multimedia console 100. The media drive 144 is connected to the I/O controller 120 via a bus, such as a Serial ATA bus or other high speed connection (e.g., IEEE 1394).

The system management controller 122 provides a variety of service functions related to assuring availability of the multimedia console 100. The audio processing unit 123 and an audio codec 132 form a corresponding audio processing pipeline with high fidelity, 3D, surround, and stereo audio processing according to aspects of the present disclosure described above. Audio data is carried between the audio processing unit 123 and the audio codec 126 via a communication link. The audio processing pipeline outputs data to the A/V port 140 for reproduction by an external audio player or device having audio capabilities.

The front panel I/O subassembly 130 supports the functionality of the power button 150 and the eject button 152, as well as any LEDs (light emitting diodes) or other indicators exposed on the outer surface of the multimedia console 100. A system power supply module 136 provides power to the components of the multimedia console 100. A fan 138 cools the circuitry within the multimedia console 100.

The CPU 101, GPU 108, memory controller 110, and various other components within the multimedia console 100 are interconnected via one or more buses, including serial and parallel buses, a memory bus, a peripheral bus, and a processor or local bus using any of a variety of bus architectures.

When the multimedia console 100 is powered on or rebooted, application data may be loaded from the system memory 143 into memory 112 and/or caches 102, 104 and executed on the CPU 101. The application may present a graphical user interface that provides a consistent user experience when navigating to different media types available on the multimedia console 100. In operation, applications and/or other media contained within the media drive 144 may be launched or played from the media drive 144 to provide additional functionalities to the multimedia console 100.

The multimedia console 100 may be operated as a standalone system by simply connecting the system to a television or other display. In this standalone mode, the multimedia console 100 may allow one or more users to interact with the system, watch movies, listen to music, and the like. However, with the integration of broadband connectivity made available through the network interface 124 or the wireless adapter 148, the multimedia console 100 may further be operated as a participant in a larger network community. In this latter scenario, the console 100 may be connected via a network to a server, for example.

Second, now turning to FIG. 2, illustrated is a block diagram representing an exemplary computing device that may be suitable for use in conjunction with implementing the subject matter disclosed above. Numerous embodiments of the present disclosure may execute on a computer. For example, the computer executable instructions that carry out the processes and methods for providing PC experiences on gaming consoles may reside and/or be executed in such a computing environment as shown in FIG. 1. The computing system environment 220 is only one example of a suitable computing environment and is not intended to suggest any limitation as to the scope of use or functionality of the presently disclosed subject matter. Neither should the computing environment 220 be interpreted as having any dependency or requirement relating to any one or combination of components illustrated in the exemplary operating environment 220. In some embodiments the various depicted computing elements may include circuitry configured to instantiate specific aspects of the present disclosure. For example, the term circuitry used in the disclosure can include specialized hardware components configured to perform function(s) by firmware or switches. In other examples embodiments the term circuitry can include a general purpose processing unit, memory, etc., configured by software instructions that embody logic operable to perform function(s). In example embodiments where circuitry includes a combination of hardware and software, an implementer may write source code embodying logic and the source code can be compiled into machine readable code that can be processed by the general purpose processing unit. Since one skilled in the art can appreciate that the state of the art has evolved to a point where there is little difference between hardware, software, or a combination of hardware/software, the selection of hardware versus software to effectuate specific functions is a design choice left to an implementer. More specifically, one of skill in the art can appreciate that a software process can be transformed into an equivalent hardware structure, and a hardware structure can itself be transformed into an equivalent software process. Thus, the selection of a hardware implementation versus a software implementation is one of design choice and left to the implementer.

Computer 241 typically includes a variety of computer readable media. Computer readable media can be any available media that can be accessed by computer 241 and includes both volatile and nonvolatile media, removable and non-removable media. The system memory 222 includes computer storage media in the form of volatile and/or nonvolatile memory such as read only memory (ROM) 223 and random access memory (RAM) 260. A basic input/output system 224 (BIOS), containing the basic routines that help to transfer information between elements within computer 241, such as during start-up, is typically stored in ROM 223. RAM 260 typically contains data and/or program modules that are immediately accessible to and/or presently being operated on by processing unit 259. By way of example, and not limitation, FIG. 2 illustrates operating system 225, application programs 226, other program modules 227, and program data 228.

The computer 241 may also include other removable/non-removable, volatile/nonvolatile computer storage media. By way of example only, FIG. 2 illustrates a hard disk drive 238 that reads from or writes to non-removable, nonvolatile magnetic media, a magnetic disk drive 239 that reads from or writes to a removable, nonvolatile magnetic disk 254, and an optical disk drive 240 that reads from or writes to a removable, nonvolatile optical disk 253 such as a CD ROM or other optical media. Other removable/non-removable, volatile/nonvolatile computer storage media that can be used in the exemplary operating environment include, but are not limited to, magnetic tape cassettes, flash memory cards, digital versatile disks, digital video tape, solid state RAM, solid state ROM, and the like. The hard disk drive 238 is typically connected to the system bus 221 through an non-removable memory interface such as interface 234, and magnetic disk drive 239 and optical disk drive 240 are typically connected to the system bus 221 by a removable memory interface, such as interface 235.

The drives and their associated computer storage media discussed above and illustrated in FIG. 2, provide storage of computer readable instructions, data structures, program modules and other data for the computer 241. In FIG. 2, for example, hard disk drive 238 is illustrated as storing operating system 258, application programs 257, other program modules 256, and program data 255. Note that these components can either be the same as or different from operating system 225, application programs 226, other program modules 227, and program data 228. Operating system 258, application programs 257, other program modules 256, and program data 255 are given different numbers here to illustrate that, at a minimum, they are different copies. A user may enter commands and information into the computer 241 through input devices such as a keyboard 251 and pointing device 252, commonly referred to as a mouse, trackball or touch pad. Other input devices (not shown) may include a microphone, joystick, game pad, satellite dish, scanner, or the like. These and other input devices are often connected to the processing unit 259 through a user input interface 236 that is coupled to the system bus, but may be connected by other interface and bus structures, such as a parallel port, game port or a universal serial bus (USB). A monitor 242 or other type of display device is also connected to the system bus 221 via an interface, such as a video interface 232. In addition to the monitor, computers may also include other peripheral output devices such as speakers 244 and printer 243, which may be connected through a output peripheral interface 233.

The computer 241 may operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 246. The remote computer 246 may be a personal computer, a server, a router, a network PC, a peer device or other common network node, and typically includes many or all of the elements described above relative to the computer 241, although only a memory storage device 247 has been illustrated in FIG. 2. The logical connections depicted in FIG. 2 include a local area network (LAN) 245 and a wide area network (WAN) 249, but may also include other networks. Such networking environments are commonplace in offices, enterprise-wide computer networks, intranets and the Internet.

When used in a LAN networking environment, the computer 241 is connected to the LAN 245 through a network interface or adapter 237. When used in a WAN networking environment, the computer 241 typically includes a modem 250 or other means for establishing communications over the WAN 249, such as the Internet. The modem 250, which may be internal or external, may be connected to the system bus 221 via the user input interface 236, or other appropriate mechanism. In a networked environment, program modules depicted relative to the computer 241, or portions thereof, may be stored in the remote memory storage device. By way of example, and not limitation, FIG. 2 illustrates remote application programs 248 as residing on memory device 247. It will be appreciated that the network connections shown are exemplary and other means of establishing a communications link between the computers may be used.

FIG. 3 provides a schematic diagram of an exemplary networked or distributed computing environment. The environment comprises computing devices 153, 156, and 157 as well as object 155 and database 158. Each of these entities 153, 155, 156, 157, and 158 may comprise or make use of programs, methods, data stores, programmable logic, etc. The entities 153, 155, 156, 157, and 158 may span portions of the same or different devices such as PDAs, audio/video devices, MP3 players, smart phones, DVD players, cable box tuners, or just about any computing devices capable of remoted content provided by server PCs. Each entity 153, 155, 156, 157, and 158 can communicate with another entity 153, 155, 156, 157, and 158 by way of the communications network 154. In this regard, any entity may be responsible for the maintenance and updating of a database 158 or other storage element.

This network 154 may itself comprise other computing entities that provide services to the system of FIG. 3, and may itself represent multiple interconnected networks. In accordance with an aspect of the presently disclosed subject matter, each entity 153, 155, 156, 157, and 158 may contain discrete functional program modules that might make use of an API, or other object, software, firmware and/or hardware, to request services of one or more of the other entities 153, 155, 156, 157, and 158.

It can also be appreciated that an object, such as 155, may be hosted on another computing device 156. Thus, although the physical environment depicted may show the connected devices as computers, such illustration is merely exemplary and the physical environment may alternatively be depicted or described comprising various digital devices such as PDAs, televisions, MP3 players, etc., software objects such as interfaces, COM objects and the like.

There are a variety of systems, components, and network configurations that support distributed computing environments. For example, computing systems may be connected together by wired or wireless systems, by local networks or widely distributed networks. Currently, many networks are coupled to the Internet, which provides an infrastructure for widely distributed computing and encompasses many different networks. Any such infrastructures, whether coupled to the Internet or not, may be used in conjunction with the systems and methods provided.

A network infrastructure may enable a host of network topologies such as client/server, peer-to-peer, or hybrid architectures. The “client” is a member of a class or group that uses the services of another class or group to which it is not related. In computing, a client is a process, i.e., roughly a set of instructions or tasks, that requests a service provided by another program. The client process utilizes the requested service without having to “know” any working details about the other program or the service itself. In a client/server architecture, particularly a networked system, a client is usually a computer that accesses shared network resources provided by another computer, e.g., a server. In the example of FIG. 3, any entity 153, 155, 156, 157, and 158 can be considered a client, a server, or both, depending on the circumstances. And, moreover, regarding the entertainment console, it can be a client to a server.

A server is typically, though not necessarily, a remote computer system accessible over a remote or local network, such as the Internet. The client process may be active in a first computer system, and the server process may be active in a second computer system, communicating with one another over a communications medium, thus providing distributed functionality and allowing multiple clients to take advantage of the information-gathering capabilities of the server. Any software objects may be distributed across multiple computing devices or objects.

Client(s) and server(s) communicate with one another utilizing the functionality provided by protocol layer(s). For example, HyperText Transfer Protocol (HTTP) is a common protocol that is used in conjunction with the World Wide Web (WWW), or “the Web.” Typically, a computer network address such as an Internet Protocol (IP) address or other reference such as a Universal Resource Locator (URL) can be used to identify the server or client computers to each other. The network address can be referred to as a URL address. Communication can be provided over a communications medium, e.g., client(s) and server(s) may be coupled to one another via TCP/IP connection(s) for high-capacity communication.

In light of the diverse computing environments that may be built according to the general framework provided in FIG. 3 and the further diversification that can occur in computing in a network environment such as that of FIG. 3, the systems and methods provided herein cannot be construed as limited in any way to a particular computing architecture or operating system. Instead, the presently disclosed subject matter should not be limited to any single embodiment, but rather should be construed in breadth and scope in accordance with the appended claims. Thus, for example, although game consoles and server PCs have been discussed, just as easily full desktops could be remoted to smart phones as a means to access data and functionality that is otherwise unavailable to smart phones.

Finally, it should also be noted that the various techniques described herein may be implemented in connection with hardware or software or, where appropriate, with a combination of both. Thus, the methods, computer readable media, and systems of the presently disclosed subject matter, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other machine-readable storage medium, where, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the subject matter.

In the case of program code execution on programmable computers, the computing device may generally include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. One or more programs that may utilize the creation and/or implementation of domain-specific programming models aspects of the present disclosure, e.g., through the use of a data processing API or the like, are preferably implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language, and combined with hardware implementations.

An SPI Protocol

Various systems, methods, and computer readable instructions are disclosed herein for providing a platform to support the development of new accessories for video game and entertainment systems. To limit the number of IC pins needed to support inter-processor communications, a simple serial interface may be used. In particular, to provide a common interface with as many off-the-shelf CPU parts as possible and to support the required data traffic, a Serial Peripheral Interface (SPI) based design may be implemented.

SPI is an interface that enables the serial exchange of data between a master and a slave device. SPI typically uses a synchronous protocol, where transmitting and receiving is guided by a clock signal generated by master microcontroller. The SPI interface allows the connection of several SPI devices while a master selects each device with a CS (Chip Select) signal.

SPI typically comprises four signal wires:

Master Out Slave In (MOSI)

Master In Slave Out (MISO)

Serial Clock (SCLK or SCK)

Chip Select (CS)

SPI is a synchronous serial data link standard. Devices communicate in a master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual chip select lines.

During each SPI clock cycle, a full duplex data transmission occurs, in which the master sends a bit on the MOSI line, the slave reads the bit from that same line, the slave sends a bit on the MISO line, and the master reads it from that same line. Transmissions typically involve two shift registers of a given word size, such as eight bits, one in the master and one in the slave. The shift registers are connected in a ring configuration. Data is typically shifted out with the most significant bit first, while shifting a new least significant bit into the same register. After that register has been shifted out, the master and slave have exchanged register values. The process may then repeat as needed.

In one exemplary and non-limiting aspect of the present disclosure, a smart transceiver device may be provided to support the rapid development of new wireless accessories for gaming platforms. In an embodiment, a smart transceiver may provide receiver and transmitter functions for physical and link wireless communications layers. In particular, the PHY and Link layers of a wireless protocol stack, and wireless protocol functionality for such a device may be implemented in a wireless application specific integrated circuit (ASIC). In one embodiment, the smart transceiver may be the slave and a master control application may be the master of an SPI bus.

In an embodiment, wireless communication may be provided using a frequency hopping digital radio protocol with time-division multiplexed access (TDMA) granting radio time for each wireless accessory. The unlicensed worldwide 2.4 GHz Industrial Scientific Medical (ISM) radio band may be utilized. A minimum of external components may be needed to implement a complete Frequency Hopping Spread Spectrum (FHSS) 2.4 GHz ISM band digital radio transceiver compliant with worldwide regulatory requirements. It should be appreciated that although a wireless SPI interface is used in the following examples, the embodiments disclosed herein are applicable to both wireless and wired implementations of an SPI interface.

As noted above, there are a number of shortcomings with the standard SPI design. To address one of the shortcomings, a method of selecting an operational mode using the limited number of pins is desirable. The operational modes relate to which is the active clock edge and to the phase of the serial data line. In one embodiment, four different operational modes may be used, and both devices at the interface may agree to a mode before starting communications. Such agreement can be accomplished by many methods but the methods typically require the use of additional IC pins.

In another embodiment, only one mode may be used and the master device supports the selected mode. However, such an approach will likely limit flexibility within the platform. A method is disclosed that may not require the use of additional pins and may be accomplished with the standard SPI pins.

In a preferred embodiment, a method for selecting the mode used by the smart transceiver may begin right after an IC reset. The smart transceiver may start up in a “Mode Detect” state. The SPI port may then wait for a Mode byte to be sent from the master control application. The Mode byte may then be sent in the correct mode that the master control application wishes to use. The smart transceiver may measure the Mode byte to determine which of the four modes was used to send the Mode byte. In one embodiment, the Mode byte may be detected three times to ensure proper detection. The Mode byte may be repeatedly transmitted until the smart transceiver responds to the Mode byte by returning an acknowledgement byte. In one embodiment, the acknowledgement byte is the 0x00 byte. When the master control application receives the acknowledgement, the Mode Detect phase of the SPI bus may be considered completed, and the smart transceiver may now operate in the correct SPI operating mode.

An example of the transaction is shown in FIG. 4. As depicted in the figure, at t0 initialization starts after a hardware reset. The transceiver SPI indicates its reset state by sending 0xFF on MISO and by driving low level on D_AVAIL#. The Master sends at least 3 times mode byte on MOSI. At t1, the transceiver has detected the “mode byte” and starts to send 0x00 on MISO for acknowledgement. At t2, the Master has detected 0x00 on MISO and stops sending the “mode byte”. The SPI-Mode initialization is finished. At t3, D_AVAIL# is set to a high level if no data transmission is required. Finally, at t4, SPI normal operation can begin, and normal communication between the Master and Transceiver starts.

FIG. 5 illustrates an exemplary method of selecting an operational mode. In operation 500, the smart transceiver has been reset. In operation 510, the smart transceiver starts up in a “Mode Detect” state. In operation 520, the SPI port waits for a Mode byte to be sent from the master control application. In operation 530, the Mode byte is sent in the correct mode that the master control application wishes to use. In operation 540, the smart transceiver receives the Mode byte. In operation 550, the smart transceiver measures the Mode byte to determine which of the four modes was used to send the Mode byte. In operation 560, additional Mode bytes may be received to ensure proper detection. In operation 570, the smart transceiver returns an acknowledgement byte. In operation 580, the master control application receives the acknowledgement, the Mode Detect phase of the SPI bus may be considered completed, and the smart transceiver may now operate in the correct SPI operating mode.

Another shortcoming of a standard SPI interface relates to the need of a Chip Select signal. The Chip Select signal is normally used if the bus is shared between multiple slave devices. In a video game system platform, only one slave device may be desired. If the Chip Select signal is not used then the signal may be tied to an always active state. However, without a Chip Select signal, proper byte framing on the bus must be addressed. Each transfer of data may be defined as the movement of one byte of data. If a clock edge is missed or an extra clock edge created and no method exists to define the correct end of the byte transfer, the Master and Slave may become un-synchronized and self-recovery may not be possible. In an embodiment, a method that enables the restoration of frame timing on the SPI bus without resetting the smart transceiver is disclosed.

In one embodiment, a frame resynchronization procedure may be initiated when a master control application detects that the messages being received from the smart transceiver are not valid. Detection of an invalid message may be done in a number of ways. One method is to determine that an undefined command was received. A second method is to determine that a command was sent but no response was received. A third method is to determine if the frame length field is not valid.

When a Frame error has been detected, the master control application may command the smart transceiver to enter a mode in which the transceiver can reset its mode status. The slave device may also detect errors using similar approaches, i.e. illegal command and length not valid. If these conditions occur, the master device may reset the interface. In an embodiment, the master control application may repeatedly send an SPI reset command until the master receives an acknowledgement from the smart transceiver. In one embodiment the reset command may be 0xFF. The acknowledgement may also be 0xFF with the Data Available interrupt line active, which indicates that the smart transceiver has data to send but is only sending an invalid command (the 0xFF command byte may be reserved during normal use). By using this method, the master control application now knows that the smart transceiver SPI port is back into the Mode Detect state and that it must re-initialize the SPI port. The master control application may then transmit the desired mode commands. The smart transceiver may then receive the correct mode command, detect the correct mode status, and respond with an acknowledgement that the mode has been received. In an embodiment, the mode status acknowledgement may be 0x00. At this point, the master control application and the smart transceiver are synchronized. Once the master control receives the acknowledgement, the master may stop transmitting the mode command. At this point, the master control application and the smart transceiver are synchronized.

An example of the Frame Resynchronization sequence is shown in FIG. 6. As depicted in the figure, at t0 the master control application has detected a frame alignment error and starts to send the reset command 0xFF on MOSI continuously. At t1, the smart transceiver has finished its last frame. At t2, the smart transceiver has detected the reset command on MOSI (0xFF), starts sending 0xFF on MISO. At t3, the master control application has detected the acknowledge from smart transceiver (MISO=0xFF and D_AVAIL#=,0′) and starts to send the mode bytes. At t4, the smart transceiver has detected and locked on the mode byte and starts to send 0x00 on MISO as acknowledgement. Now the master control application and the smart transceiver are frame aligned again. Finally, at t5, the master control application has detected 0x00 on MISO and stops sending the “mode byte.”

FIG. 7 illustrates an exemplary method of frame resynchronization. In operation 700, a frame resynchronization procedure may be initiated when a master control application detects that the messages being received from the smart transceiver are not valid. As mentioned above, a number of methods can be used to determine if an invalid message was received.

When a frame error has been detected, in operation 710 the master control application may command the smart transceiver to enter a mode in which the transceiver can reset its mode status. In an embodiment, in operation 720 the master control application may repeatedly send an SPI reset command until it receives an acknowledgement 730 from the smart transceiver. In operation 740 the master control application may then transmit the mode commands. In operation 750, the smart transceiver may receive the mode command. In operation 760, the smart transceiver may detect and lock on the mode status. In operation 770, the smart transceiver may respond with an acknowledgement that the mode has been received. In an embodiment, the mode status acknowledgement may be 0x00. At this point, the master control application and the smart transceiver are synchronized. Once the master control receives the acknowledgement, the master may stop transmitting the mode command 780.

Turning now to FIG. 7a, illustrated is an exemplary system incorporating aspects of frame resynchronization. An SPI device 1786 and SPI device 2788 may be in communication via a full duplex Serial Peripheral Interface (SPI) link. As discussed, one device may be a master device, and the other device may be a slave device. Circuitry 796 may reset SPI Device 1786. Circuitry 790 may configure SPI Device 1786 to enter a mode detect state. Circuitry 792 may be configured to receive at least one mode message from the SPI Device 2788 via the full duplex SPI link using a framed messaging protocol overlaid on the SPI link. The messages may further comprise a header and a variable length payload. The header may comprise a command field and a length field, and the length field may be representative of a size of the variable length payload. Circuitry 794 may be configured to enable SPI Device 1786 to return an acknowledgment message to SPI Device 2788.

A further shortcoming of a standard SPI interface is that data transfers are limited to eight bits at one time. Because many applications may require higher command and data transfer capability, a higher level protocol is needed that still retains the advantages of a serial interface. In consideration of an efficient control/data transport method across the SPI bus with full duplex data transfer, in various embodiments a frame based SPI protocol is disclosed that may be used to provide control and data transfer to and from the smart transceiver device. In particular, an exemplary format for the protocol, the commands, and responses is disclosed. In an embodiment, each frame may consist of a two byte header with a variable payload length. The header may comprise two parts—a command byte and a length byte. The length of the payload may be dependent upon the specific command, and the longest packet may define the length of the transfer. FIG. 8 provides and exemplary illustration of a typical data transfer.

Because the disclosed protocol comprises a full duplex interface, if one device has no information to transfer, the device may send an idle command. The disclosed protocol may maintain a master/slave structure, with a master control application typically controlling all transactions, and the master control application transferring data whenever it has a message ready to transmit. The smart transceiver may act as the slave device and may return a reply indicating either the result of the request, compliance to the command, or an indication of the occurrence of an event from a previous request. The smart transceiver may further generate an interrupt to the master control application indicating that a message is ready to be read by the master.

The disclosed protocol may further comprise the following rules that apply to a frame transaction. First, the chip select may be in an active state. Second, a header may always be transmitted first on both ends of the link. If one end does not have a valid message to transmit, the command field may be set to be 0x00. Third, the longest frame (master to slave or slave to master) may be used to define the length of the transfer. Fourth, if one side has more than one packet to send, the independent messages may be appended together within the same frame.

The cases depicted in the table below are all exemplary valid transfers.

Case
Master

Slave

No.
data
no data
data
no data

1
X

X

2

X¹⁾

X

3
X

X

4

X
X

5
X²⁾

X²⁾

6
X²⁾

X¹⁾

7

X³⁾
X²⁾

¹⁾Single Command

²⁾Multiple Data

³⁾Dummy Command

FIGS. 9-15 illustrate exemplary timing diagrams depicting bus transfers for the scenarios outlined in the table. FIG. 9 depicts a master with data to transmit and the slave with a command to transmit but no data. FIG. 10 depicts the master with a command to transmit but no data and the slave with no data. FIG. 11 depicts the master with data to transmit and the slave with data to transmit. FIG. 12 depicts the master with a command to transmit but no data and the slave with data. FIG. 13 depicts the master with multiple data packets and the slave with multiple data packets. FIG. 14 depicts the master with multiple data packets and the slave with a single data packet to transmit. Finally, FIG. 15 depicts the master with no data to transmit, and the slave with multiple data packets.

Lastly, while the present disclosure has been described in connection with the preferred aspects, as illustrated in the various figures, it is understood that other similar aspects may be used or modifications and additions may be made to the described aspects for performing the same function of the present disclosure without deviating there from. For example, in various aspects of the disclosure, a protocol for a serial peripheral interface was disclosed. However, other equivalent mechanisms to these described aspects are also contemplated by the teachings herein, including those applicable to both wired and wireless implementations. Therefore, the present disclosure should not be limited to any single aspect, but rather construed in breadth and scope in accordance with the appended claims.

Serial Peripheral Interface for a Transceiver Integrated Circuit

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