Serial processing of video signals using a programmable hardware device

Abstract

Serial processing of video signals is efficiently carried out by the method and system which makes use of specifically configured bitstream processors. The particular bitstream processors utilized include specifically configured decoder blocks and encoder blocks which are uniquely designed to carry out the serial processing tasks necessary for video encoding and decoding operations. These encoder and decoder blocks are uniquely programmed within the bitstream processor, thus providing specific capabilities most beneficial when dealing with video data.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects and advantages of the present invention will be seen by studying the following detailed description, in conjunction with the drawings in which:

FIG. 1 illustrates a block diagram of the video processing system;

FIG. 2 illustrates schematically the data flow during encoding operations;

FIG. 3 illustrates schematically the data flow during decoding operations;

FIG. 4 is a block diagram of a decoder block utilized within the bitstream processor;

FIG. 5 is a block diagram of an encoder utilized in the bitstream processor; and

FIG. 6 is a schematic illustration showing a block remapping operation undertaken by the system controller.

Claims

1. A video processing system for serial processing of a/v data, comprising: a system controlleran a/v input module for receiving a/v signals, the a/v input module having an output coupled to the system controller for outputting a/v signals;an a/v output module for outputting a/v signals, the a/v output module having an input coupled to the system controller for receiving a/v signals;a parallel processor for processing a/v data coupled to the system controller; anda bitstream processor for performing serial data processing operations coupled to the system controller, the bitstream processor further comprising:at least one decoder block for decoding video data, wherein each decoder block comprises a fifo register for receiving an encoded video stream and serially storing in an ordered manner, a variable length decoder for operating on the encoded video stream to generate a stream of video data having fixed data size, a coefficient remapper for receiving the fixed size video data stream and determining coefficient information and storing in a block memory a block bitstream video data, wherein the block of bitstream video data corresponds to a predetermined block of pixel data, and a differential decoder for decoding motion vectors and producing a decoded video data stream for transfer to the parallel processor for further processing; andat least one encoder block for encoding video data, wherein each encoder block comprises a memory for receiving parallel encoded video data from the parallel processor and storing one block of video data, a motion vector encoder for applying motion vectors to the block of video data, a coefficient remapping module for attaching coefficient data to the block of pixel data, a variable length encoder for coding block of pixel data thus creating video data having variable length code words corresponding to the pixels, and a fifo register for receiving the variable length and producing a serial bitstream of encoded video data.

2. The system of claim 1 wherein the variable length encoder is loaded with a predetermined code map.

3. The system of claim 1 wherein the variable length decoder is loaded with a predetermined code map.