Claims
- 1. A serial-to-parallel converter consisting solely of no more than a specified number n of memory cells connected in series and adapted to successively shift input data therethrough in synchronism with a shift clock, and n latch circuits individually interconnected with said memory cells with means connected to said latch circuits to receive a latch signal so that application of said latch signal to said latch circuits alone causes the contents of said memory cells to be individually transferred to said latch circuits, said memory cells being provided with input terminals through which said memory cells directly receive a signal for setting or resetting said memory cells together before said input data are entered.
- 2. The serial-to-parallel converter of claim 1 wherein said memory cells comprise CMOS transistors.
- 3. The serial-to-parallel converter of claim 1 wherein output signals from said converter are unaffected by said shift clock.
- 4. The serial-to-parallel converter of claim 1 wherein each of said memory cells has a clock pulse terminal through which clock signals from said shift clock is received.
- 5. The serial-to-parallel converter of claim 1 wherein said latch circuits output the contents thereof in parallel.
Priority Claims (1)
Number |
Date |
Country |
Kind |
59-5458[U] |
Jan 1984 |
JPX |
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Parent Case Info
This is a continuation of application Ser. No. 691,268 filed Jan. 14, 1985.
US Referenced Citations (11)
Non-Patent Literature Citations (1)
Entry |
"Deserializer", p. 653, IBM Technical Disclosure Bulletin, vol. 14, No. 2, Jul. 1971. |
Continuations (1)
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Number |
Date |
Country |
Parent |
691268 |
Jan 1985 |
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