Patent Application
20160065394
The present invention relates generally to electrical and electronic circuitry, and more particularly relates to data communications.
It is well known that when a signal passes through a band-limited channel it will suffer waveform distortion. For example,
In a digital communication system, an eye pattern, also known as an eye diagram, provides a convenient means of evaluating the combined effects of channel noise and ISI on the performance of a baseband transmission. It is essentially a synchronized superposition of all possible realizations of a signal of interest viewed within a prescribed signaling interval (e.g., unit interval (UI)). Several system performance characteristics can be determined by analyzing an eye pattern. For example, if signals are too long, too short, poorly synchronized with the system clock, have too much undershoot or overshoot, etc., this can be readily observed from the eye pattern. An open eye pattern corresponds to minimal signal distortion, while closure of the eye pattern is generally indicative of distortion of the signal waveform due to ISI and channel noise as the data rate increases.
In accordance with an embodiment of the invention, a method for reducing a disparity between even and odd eye characteristics in recovered data includes: receiving an input serial data stream; performing independent data slicing of even and odd components in the serial data stream to generate corresponding even and odd discrete-time data samples, respectively; performing independent error slicing of even and odd components in the serial data stream to generate corresponding even and odd discrete-time error samples, respectively; deserializing the even and odd discrete-time data and error samples to generate the recovered data and recovered error, respectively; and controlling respective offsets for error slicing of the even and odd components independently so as to reduce the disparity between even and odd eye characteristics in the recovered data. Other embodiments of the invention include, but are not limited to, being manifest as a data communication apparatus, an integrated circuit including at least one data communication apparatus, a method for reducing even/odd eye disparity in a serializer/deserializer (SerDes), and an electronic system. Additional and/or other embodiments of the invention are described in the following written description, including the claims, which is to be read in connection with the accompanying drawings.
The following drawings are presented by way of example only and without limitation, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and wherein:
It is to be appreciated that the drawings described herein are presented for illustrative purposes only. Moreover, common but well-understood elements and/or features that may be useful or necessary in a commercially feasible embodiment may not be shown in order to facilitate a less hindered view of the illustrated embodiments.
Embodiments of the invention will be described herein in the context of illustrative serializer/deserializer (SerDes) receiver circuitry for use, for example, in a data communication system. It should be understood, however, that embodiments of the invention are not limited to these or any other particular circuit arrangements or applications. Rather, embodiments of the invention are more broadly applicable to techniques for reducing an error rate in recovered data in a data communication system. In this regard, embodiments of the invention provide an apparatus and methodology for beneficially reducing a disparity between even and odd eye characteristics in a SerDes by providing independent equalization adaptation of even and odd data eyes of a received serial data stream.
It will become apparent to those skilled in the art given the teachings herein that numerous modifications can be made to the illustrative embodiments shown that are within the scope of the claimed invention. That is, no limitations with respect to the embodiments shown and described herein are intended or should be inferred.
As a preliminary matter, for purposes of clarifying and describing embodiments of the invention, the following table provides a summary of certain acronyms and their corresponding definitions, as the terms are used herein:
The local SerDes 204 includes a receiver (RX) 211 configured to receive the serial transmit data stream from the channel 206. The serial data, degraded after transmission through the channel 206, undergoes amplification by a variable gain amplifier (VGA) 212 included in the receiver 211. The serial data is enhanced using equalization by a linear equalizer (LEQ) 214 configured to compensate for potential low-pass filtering characteristics of the channel 206. The equalized serial data generated by the linear equalizer 214 is supplied to a summing node (e.g., adder) 216 where additional enhancement is implemented using a decision feedback equalizer (DFE) 218.
Subsequent to decision feedback equalization of the serial data stream, the serial data is sampled using slicers 220; slicers 220 incorporate data slicers, transition slicers and error slicers. The slicers 220 are operative to convert the serial data stream into discrete-time digital domain samples. The sampled data generated by the slicers 220 is then deserialized using a deserializer 222 coupled with an output of the slicers. Outputs generated by the deserializer 222 are used as the recovered data. The recovered data is also used to generate parameters for equalization adaptation, or other post-processing. In this regard, a receiver equalization (RXEQ) adaptation module 224 included in the receiver 211 is configured to receive at least a portion of the recovered data from the deserializer 222 and to generate, as a function of the recovered data, one or more parameters used in implementing the equalization adaptation process, for example in generating a desired offset for the error slicers 220 used in a least mean squares (LMS) adaptation algorithm and decision feedback equalization coefficients H1 through Hn, where n is an integer. Equalization coefficient H0 is supplied as a vertical offset to the error slicers 220, while one or more of the equalization coefficients H1 through Hn are supplied to the decision feedback equalizer 218, linear equalizer 214 and variable gain amplifier 212 in a closed-loop feedback arrangement.
The adaptation parameters for the remote transmitter FIR filter 210, taken as an output of the receiver equalization adaptation module 224, are supplied to link logic 226 in the local SerDes device 204 which is configured to format the transmitter FIR adaptation data for transmission by a transmitter 228 in the local SerDes to a corresponding receiver 232 in the remote SerDes 202 via a back channel 230 established between the local SerDes and the remote SerDes. The data received by the receiver 232 in the Remote SerDes 202 is then supplied to link logic 234 where it is reformatted for use by the transmitter FIR filter 210. In this manner, one or more parameters used by the transmitter FIR filter 210 in the feed-forward equalization of the serial transmit data stream are modified as a function of the data received from the local SerDes so as to configure the remote transmitter FIR filter 210 for a more optimal eye opening at the receiver 211.
In order to make the hardware design feasible for high serial data rates, the equalized serial data stream generated by the linear equalizer 214, in one or more embodiments, is split into two data paths; namely, an even data path and an odd data path. The serial data is sampled by the slicers 220 at half data rate, taking one sample from the even data path and one sample from the odd data path for each period of a sampling clock used by the slicers in generating the discrete-time digital domain samples. This approach is also used by the corresponding transmitter 208 in the remote SerDes 202. However, while this approach increases a feasibility of the hardware implementation, it also creates artifacts in the transmitted data, producing an inequality of a horizontal eye opening between the even and odd data paths due to duty cycle distortion of the half data rate (two unit interval (UI)) bit clock (as shown in
Since many of the parameters used in the transmitter and receiver of a SerDes are variable, it is desirable to set them to optimal values. One way to more optimally control the transmitter and receiver parameters, particularly in a changing and initially unpredictable environment, is to employ real-time adaptation. A standard adaptation algorithm used in a SerDes transmitter and receiver is LMS, which uses data and error samples for adaptation. An example of serial data sampling for this algorithm will be discussed below with reference to
More particularly,
The value of the vertical offset is adapted, in one or more embodiments, using the LMS algorithm to place an error slicer in the statistical middle of all data positive eye traces, or alternatively negative eye traces, at the sampling time. An LMS algorithm for H0 adaptation can be expressed in pseudo code as follows:
H
0=
where “̂” is a symbol used to represent an exclusive OR logic operation, and DiΛEsigni tests if the data, Di, has the same polarity as the error slicer offset, Esigni. The “?” symbol represents a condition placed on the equation preceding it. Specifically, if the expression (DiΛEsigni) is false, then and only then is the subsequent summation (E0∞
A gain of the VGA 212 in
H
n=
where n is an integer which represents the decision feedback coefficient number in the general sense.
LMS-based linear equalization, which is implemented, for example, in the linear equalizer 214 in the SerDes receiver 211 shown in
LEQ=
where the term Dih in equation (3) represents an average of a prescribed number of previous samples (e.g., Di-4 through Di-1). It is to be understood that embodiments of the invention are not limited to any specific number of taps used in the averaging methodology. When initially all of the receiver parameters in the local SerDes 204 are adapted to the incoming serial signal, back channel adaptation of the transmitter FIR filter 210 in the remote SerDes 202 shown in
Remote transmitter FIR filter coefficients to be adapted are typically pre- and postcursor coefficients, CM1 and CP1, respectively, where “CM1” is defined as “coefficient minus one” (i.e., precursor) and CP1 is defined as “coefficient plus one” (i.e., postcursor). With reference again to
Known methods of VGA, LEQ, and DFE adaptation do not make any distinction between even and odd eyes but rather use averaging between even and odd eyes, utilizing the same parameters for gain, analog (linear) equalization, error slicer offset, and DFE coefficients. This leads to a non-optimal placement of error slicers in the two eyes, resulting in inferior equalization adaptation in the presence of even/odd eye disparity.
In accordance with embodiments of the invention, in order to reduce the disparity between even and odd eye sizes, equalization adaptation is performed independently for even and odd data samples. It is to be appreciated that while the apparatus and methodologies described herein are applicable to a half data rate clock used in the transmitter and receiver for serialization/deserialization of the data, techniques in accordance with one or more embodiments of the invention are equally applicable to alternative (e.g., slower) clock architectures, with modifications that will become readily apparent to those skilled in the art given the teachings herein.
First, one or more embodiments of the invention split even and odd error slicer offset (H0) adaptation into separate expressions. Specifically, equation (1) above is re-written as follows:
H
0
E=
H
0
O=
where H0E represents H0 adaptation corresponding to the even eye and H0O represents H0 adaptation corresponding to the odd eye; that is, equations (4) above accumulate H0 offset separately for even and odd eyes as H0E and H0O, respectively. This allows for placement of corresponding error slicers in the statistical middle of all traces in each of the eyes independently. More optimally placed error slicers in the presence of even/odd eye disparity will provide for an enhanced LMS adaptation of at least the DFE 218 shown in
By way of example only and without limitation,
The amplified serial data generated by the VGA 404 is optionally enhanced using equalization by a linear (i.e., analog) equalizer (LEQ) 406 coupled with the VGA. In embodiments that do not employ linear equalization, the LEQ 406 can be eliminated. The linear equalizer 406 is configured to compensate for potential low-pass filtering characteristics of the channel 402 and to generate an equalized serial data stream. One or more equalization characteristics of the linear equalizer 406 are controlled as a function of a second control signal supplied to the linear equalizer. The equalized serial data generated by the linear equalizer 406 is supplied to an adder 408, or alternative summation element (e.g., summing node) which, in this embodiment, is configured to facilitate further enhancement of the serial data using, for example, decision feedback equalization, as will be described in further detail below.
Subsequent to decision feedback equalization of the serial data stream, the serial data is sampled using data slicers. In this embodiment, the serial data stream is split into separate even and odd components. The receiver 400 comprises first slicers 410, configured to convert the even components in the serial data stream into corresponding even discrete-time digital domain samples, and second slicers 412, configured to convert the odd components in the serial data stream into corresponding odd discrete-time digital domain samples. It is to be appreciated that each of the slicers 410, 412 comprises data slicers, error slicers and transition slicers. A slicing threshold in each of the error slicers 410, 412 is independently controlled by separate control signals supplied thereto. In this embodiment, error slicers in the first and second slicers 410, 412 are separately controlled; data and transition slicers need not be separately controlled since they do not contribute to vertical offset (e.g., H0 in
The even and odd sampled data generated by the even slicers 410 and odd slicers 412, respectively, are deserialized using a deserializer 414 coupled with outputs of the even and odd slicers. Samples generated by the deserializer 414 form the recovered data output of the receiver 400. Transition and data samples after deserialization are used for recovered data and phase detection used in CDR locking to the data; deserialized error samples are used for receiver adaptation.
The recovered data is used to perform decision feedback equalization to further enhance the recovered data output. Specifically, at least a portion of the recovered data is fed back to the adder 408 via a decision feedback equalizer (DFE) 416 which is coupled between the deserializer 414 and the adder in a closed loop feedback configuration. The DFE 416 uses information about previously received samples to reduce or cancel out their ISI contributions from the current decision. One or more parameters of the DFE 416 are controlled as a function of at least a fifth control signal supplied to the DFE.
The recovered data output, in this embodiment, is also used to generate control signals for equalization adaptation, or other post-processing. In this regard, the receiver 400 includes a receiver equalization (RXEQ) adaptation module 418 which is configured to receive at least a portion of the recovered data output from the deserializer 414 and to generate, as a function of the recovered data, one or more control signals used in implementing an equalization adaptation methodology, for example in generating equalization adaptation coefficients H1 through Hn, where n is an integer.
More particularly, an even equalization adaptation coefficient H0E generated by the receiver equalization adaptation module 418 is supplied to a first digital-to-analog converter (DAC) 420, which in this embodiment is an even DAC (DACE), configured to convert H0E to an analog signal which is used to form the third control signal supplied to the even slicers 410 as even error slicer offset. Likewise, an odd equalization adaptation coefficient H0O generated by the receiver equalization adaptation module 418 is supplied to a second DAC 422, which in this embodiment is an odd DAC (DACO), configured to convert H0O to an analog signal which is used to form the fourth control signal supplied to the odd slicers 412 as odd error slicer offset. Thus, separately adapted H0E and H0O coefficients are sent to the even and odd DACs 420 and 422, respectively, for converting a digital error slicer offset to respective analog control signals which are, in turn, applied to corresponding even and odd error slicers in the even and odd slicers 410 and 412. In one or more alternative embodiments, a single DAC can be utilized for even and odd conversion using, for example, a time-division multiplexing (TDM) scheme.
Other coefficients generated by the receiver equalization adaptation module 418 (e.g., coefficients H1 through Hn) are used for controlling one or more parameters of the DFE 416, the LEQ 406 and the VGA 404. Specifically, one or more control signals are used to control at least a gain of the VGA 404, the second control signal used to control one or more linear equalization parameters of the LEQ 406, and the coefficients H1 through Hn are used to control one or more decision feedback equalization parameters of the DFE 416, in accordance with one or more embodiments of the invention.
Properly placed error slicers make LMS algorithm for DFE, VGA and LEQ adaptation use correct error terms per equations (2) and (3) above because both error slicers are placed in the statistical middle between inner and outer eyes for both even and odd eyes. While the receiver architecture shown in
In order to improve the overall performance of equalization adaptation in the SerDes receiver, one or more embodiments of the invention utilize separate adaptation for even and odd DFE coefficients. Modified equations, based on equation (2) above, for split even and odd DFE coefficient adaptation are expressed as follows:
H
n
E=
H
n
O=
By way of example only and without limitation,
The amplified serial data generated by the VGA 504 is enhanced using equalization by a linear equalizer (LEQ) 506 coupled with the VGA. The linear equalizer 506 is configured to compensate for potential low-pass filtering characteristics of the channel 502 and to generate an equalized serial data stream. One or more equalization characteristics of the linear equalizer 506 are controlled as a function of a second control signal supplied to the linear equalizer. The equalized serial data generated by the linear equalizer 506 is supplied to an adder 508, or alternative summation element which, in this embodiment, is configured to facilitate further enhancement of the serial data using, for example, decision feedback equalization, as will be described in further detail below.
Subsequent to decision feedback equalization of the serial data stream, the serial data is sampled using data slicers. In this embodiment, like in the illustrative receiver 400 shown in
The even and odd sampled data generated by the even slicers 510 and odd slicers 512, respectively, are deserialized using a deserializer 514 coupled with outputs of the even and odd slicers. Samples generated by the deserializer 514 form the recovered data output of the receiver 500. As previously stated, transition and data samples after deserialization are used to generate the recovered data and phase detection used in CDR locking to the data; deserialized error samples are used for receiver adaptation.
The recovered data is used to perform decision feedback equalization to further enhance the recovered data output. Specifically, at least a portion of the recovered data is fed back to the adder 508 (even and odd) via a decision feedback equalizer (DFE) 516 which is coupled between the deserializer 514 and the adder in a closed loop feedback configuration. The DFE 516 uses information about previously received samples to reduce or cancel out their ISI contributions from the current decision. Unlike the DFE 416 in the receiver 400 of
The recovered data output is also used to generate control signals for equalization adaptation, or other post-processing. In this embodiment, the receiver 500 includes a first receiver equalization (RXEQ) adaptation module 518 which is configured to receive samples in the recovered data output from the deserializer 514 and to generate, as a function of the even error samples, a set of even equalization coefficients, H0E through HnE, used in implementing an equalization adaptation methodology. In this regard, an adaptation algorithm according to one or more embodiments of the invention utilizes data from both even and odd slicers, but even error slicer information is used for even DFE coefficients, and odd error slicer information is used for odd coefficients, as can be seen from the equations (5) above. The receiver 500 further includes a second receiver equalization (RXEQ) adaptation module 520 which is configured to receive data samples and odd error samples in the recovered data output from the deserializer 514 and to generate, as a function of the odd error samples, a set of odd equalization coefficients, H0O through HnO, used in implementing the equalization adaptation methodology.
More particularly, an even equalization adaptation coefficient H0E generated by the even receiver equalization adaptation module 518 is supplied to a first digital-to-analog converter (DAC) 522, which in this embodiment is an even DAC (DACE), configured to convert H0E to an analog signal which is used to control the even error slicers 510. Likewise, an odd equalization adaptation coefficient H0O generated by the odd receiver equalization adaptation module 520 is supplied to a second DAC 524, which in this embodiment is an odd DAC (DACO), configured to convert H0O to an analog signal which is used to control the odd error slicers 512. Thus, separately adapted H0E and H0O coefficients are sent to the even and odd DACs 522 and 524, respectively, for converting a digital error slicer offset to respective analog control signals which are, in turn, applied to corresponding even and odd error slicers in the even and odd slicers 510 and 512. In one or more alternative embodiments, a single DAC can be utilized for even and odd conversion using, for example, a TDM scheme.
Other coefficients generated by the even and odd receiver equalization adaptation modules 518 and 520 are used for controlling one or more parameters of the DFE 516, the LEQ 506 and the VGA 504. Specifically, one or more coefficients in the set of even coefficients H1E through HnE generated by the even receiver equalization adaptation module 518 form the first set of control signals used to control one or more decision feedback equalization parameters of the DFE 516. These digital even coefficients H1E through HnE are first converted to corresponding analog signals using a third DAC 526, which in this embodiment is an even DAC (DACE), before being supplied to the DFE 516. Likewise, one or more coefficients in the set of odd coefficients H1O through HnO generated by the odd receiver equalization adaptation module 520 form the second set of control signals used to control one or more decision feedback equalization parameters of the DFE 516. These digital odd coefficients H1O through HnO are first converted to corresponding analog signals using a fourth DAC 528, which in this embodiment is an odd DAC (DACO), before being supplied to the DFE 516. As in the case of DACs 522 and 524, DACs 526 and 528 may, in other embodiments, be replaced by a single DAC which is shared between the even and odd samples, such as, for example, using TDM or an alternative multiplexing scheme. One or more of the control signals also form the first control signal used to control at least a gain of the VGA 504, and the second control signal used to control one or more linear equalization parameters of the LEQ 506. Since, in this embodiment, the VGA 504 and LEQ 506 are applied to both even and odd eyes without distinction, the control signals generated by the even and odd receiver equalization adaptation modules 518 and 520 are averaged.
There are at least two techniques for applying H1 DFE that are suitable for use in accordance with embodiments of the invention; namely, rolled DFE and unrolled DFE. For the rolled DFE methodology, the H1 value is added to or subtracted from the analog serial signal on-the-fly. Specifically, according to one or more embodiments of the invention, the value of the H1E even coefficient will be added or subtracted for even eye samples, and the value of the H1O odd coefficient will be added or subtracted for odd eye samples. The unrolled DFE technique employs two data slicers offset by ±H1. Post processing of data makes a decision as to which data slicer to use for data recovery based on the digital value of the previous sample. Specifically, for unrolled DFE, one or more embodiments of the invention will use ±H1E slicers for even eye samples, and ±H1O slicers for odd eye samples.
As will be appreciated by those skilled in the art, at least a portion of embodiments of the present invention may be implemented as an apparatus, system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to as a “circuit,” “module,” “block,” or “system.” Furthermore, embodiments of the present invention may take the form of a computer program product embodied in one or more non-transitory machine-readable medium(s) having machine-readable program code embodied thereon.
One or more embodiments of the invention, or elements thereof, can be implemented in the form of an apparatus including a memory and at least one processor coupled with the memory and operative to perform exemplary method steps in accordance with embodiments of the invention.
One or more embodiments of the invention make use of software running on a general purpose computer or workstation which, when configured by the software, is transformed into a special purpose machine operative to perform methods in accordance with embodiments described herein. With reference to
Accordingly, computer software including instructions or code for performing methodologies according to embodiments of the invention, as described herein, may be stored in one or more of the associated memory devices (for example, ROM, fixed or removable memory) and, when ready to be utilized, loaded in part or in whole (for example, into RAM) and implemented by a CPU. Such software could include, but is not limited to, firmware, resident software, microcode, and the like.
A data processing system suitable for storing and/or executing program code will include at least one processor 602 coupled directly or indirectly with memory elements 604 through a system bus 610. The memory elements can include local memory employed during actual implementation of the program code, bulk storage, cache memories and embedded memory which provide temporary storage of at least a portion of program code in order to reduce the number of times the code must be retrieved from bulk storage during implementation.
Input/output or I/O devices (including but not limited to keyboards 608, displays 606, pointing devices, and the like) can be coupled to the system either directly (such as via bus 610) or through intervening I/O controllers (omitted for clarity).
Network adapters such as network interface 614 are also coupled with the system, in one or more embodiments of the invention, to enable the data processing system to become coupled with other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters.
As noted, one or more embodiments of the present invention may take the form of a computer program product embodied in one or more non-transitory machine- or computer-readable medium(s) having computer-readable program code embodied thereon. Any combination of one or more computer-readable medium(s) may be utilized. The computer-readable medium may be a computer readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Media block 618 is a non-limiting example. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In one or more embodiments, a computer-readable storage medium is any tangible medium that can contain or store a program, in a non-transitory manner, for use by or in connection with an instruction execution system, apparatus, or device.
Computer program code for carrying out operations according to one or more embodiments of the invention are written in any combination of one or more programming languages, including an object-oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
The computer program code, in one or more embodiments, is loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing functions/acts specified in a flowchart and/or block diagram block or blocks.
The block diagrams in the figures depict illustrative architectures, functionality, and operation of implementations of systems, methods and computer program products according to embodiments of the present invention. In this regard, each block shown in the block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing specified functions. It should also be noted that, in one or more embodiments, functions represented by the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be appreciated that each block of the block diagrams, and combinations of blocks in the block diagrams, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
It should be understood that any of the methods described herein can include an additional step of providing a system comprising distinct software modules embodied on a non-transitory computer-readable storage medium; the modules include, in one or more embodiments, any or all of the elements depicted in the block diagrams and/or described herein; by way of example and without limitation, a linear equalizer, adder, data slicer, deserializer, serializer, decision feedback equalizer and equalization adaptation module. The method steps can then be carried out using the distinct software modules and/or sub-modules of the system, executing on one or more hardware processors 602. Further, a computer program product can include a computer-readable storage medium with code adapted to be implemented to carry out one or more method steps described herein, including the provision of the system with the distinct software modules.
In any case, it should be understood that the components illustrated herein may be implemented in various forms of hardware, software, or combinations thereof; for example, application-specific integrated circuits (ASICs), functional circuitry, one or more appropriately programmed general purpose digital computers with associated memory, and the like. Given the teachings of the invention provided herein, one of ordinary skill in the related art will be able to contemplate other implementations of the components of the invention.
In an integrated circuit implementation of one or more embodiments of the invention, multiple identical die are typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Each such die may include a device described herein, and may include other structures and/or circuits. The individual dies are cut or diced from the wafer, then packaged as integrated circuits. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Any of the exemplary circuits illustrated in the accompanying figures, or portions thereof, may be part of an integrated circuit. Integrated circuits so manufactured are considered part of this invention.
The illustrations of embodiments of the invention described herein are intended to provide a general understanding of the structure of various embodiments, and they are not intended to serve as a complete description of all the elements and features of apparatus and systems that might make use of the structures described herein. Many other embodiments will become apparent to those skilled in the art given the teachings herein; other embodiments are utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of this disclosure. The drawings are also merely representational and are not drawn to scale. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Embodiments of the invention are referred to herein, individually and/or collectively, by the term “embodiment” merely for convenience and without intending to limit the scope of this application to any single embodiment or inventive concept if more than one is, in fact, shown. Thus, although specific embodiments have been illustrated and described herein, it should be understood that an arrangement achieving the same purpose can be substituted for the specific embodiment(s) shown; that is, this disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will become apparent to those of skill in the art given the teachings herein.
The abstract is provided to comply with 37 C.F.R. §1.72(b), which requires an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Written Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, inventive subject matter lies in less than all features of a single embodiment. Thus the following claims are hereby incorporated into the Written Description, with each claim standing on its own as separately claimed subject matter.
Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of embodiments of the invention. Although illustrative embodiments of the invention have been described herein with reference to the accompanying drawings, it is to be understood that embodiments of the invention are not limited to those precise embodiments, and that various other changes and modifications are made therein by one skilled in the art without departing from the scope of the appended claims.
