Patent Application
20250053536
The present application claims the priority of the Chinese patent application 202210466930.0 titled “SERVER AND SERVER MANAGEMENT SYSTEM THEREFOR” filed in China National Intellectual Property Administration on Apr. 29, 2022, which is incorporated herein by reference in their entirety.
The present disclosure relates to the field of servers, and in particular to a server management system and a server.
In the past, the server management unit has been included in the server mainboard. Modularizing the server management unit and separating it from the mainboard of the server have obvious advantages. With the continuous updating and iteration of CPU technology for the server, server applications are constantly being innovated. In the future, the integration of the central processing unit (CPU) Southbridge chip and the CPU will result in the removal of low-speed interfaces such as the universal serial bus (USB). The CPU partitioning application enables two CPUs to run the operating system separately. For the new CPU design, there is a lack of a mature server management system in the conventional technology.
The objective of the present application is to provide a server management system. The server management system in the present application may be applied to a future solution of the CPU partitioning application without the USB interface, and has a simple structure and strong stability. Another objective of the present application is to provide a server including the above server management system. The server management system in the present application may be applied to a future solution of the CPU partitioning application without the USB interface, and has a simple structure and strong stability.
In order to solve the above technical problem, the present application provides a server management system, including:
In some embodiments, the baseboard management control apparatus includes:
In some embodiments, the control module is further connected to a low voltage differential signaling (LVDS) interface of a mainboard:
In some embodiments, the server management system further includes:
In some embodiments, the control module is further connected to an improved inter integrated circuit (I3C) interface of the CPU; and
In some embodiments, the gating switch includes:
In some embodiments, the server management system further includes a third USB interface connected to the USB controller; and
In some embodiments, the control module is a field programmable gate array (FPGA).
In some embodiments, the trusted root security management apparatus includes:
In order to solve the above technical problem, the present application also provides a server including the above server management system.
The present application provides a server management system. The server management system in the present application may assist two CPUs in startup, may receive PCIe signals sent by the two CPUs for display of the operating system interface, and may also send the received keyboard and mouse instruction to the CPU connected to the gating switch through the USB controller, thereby realizing the keyboard and mouse application. When the USB controller performs mutual conversion between the USB signal and the PCIe signal, the communication between the CPUs connected to the gating switch is implemented through the first USB interface. It may be seen that the present application may be applied to a future solution of CPU partitioning application in which the USB interface is removed, and has a simple structure and strong stability.
The present application also provides a server, which has the same beneficial effects as the above server management system.
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure or the prior art, the figures that are required to describe the embodiments or the prior art may be briefly introduced below: Apparently, the figures that are described below are embodiments of the present disclosure, and a person skilled in the art may obtain other 20) figures according to these figures without paying creative work.
The core of the present application is to provide a server management system. The server management system in the present application may be applied to a future solution for the CPU partitioning application without the USB interface. It has a simple structure and strong stability. Another core of the present application is to provide a server including the above server management system. The server management system in the present application may be applied to a future solution for the CPU partitioning application without the USB interface. It has a simple structure and strong stability.
In order to make the objects, the technical solutions and the advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure may be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. Apparently, the described embodiments are merely certain embodiments of the present disclosure, rather than all of the embodiments. All of the other embodiments that a person skilled in the art obtains on the basis of the embodiments of the present disclosure without paying creative work fall within the protection scope of the present disclosure.
Referring to
Refer to
At present. CPU products are updated and iterated rapidly. In the future, the CPU Southbridge chip will be integrated with the CPU, which results in the removal of low-speed interfaces such as the USB. The existing USB solution may not be adapted to a new generation of CPUs. With the increasing demand for reliable operations of low-energy consumption applications in the data center, the concept of CPU partitioning application has been proposed. However, the existing server management solution does not support the CPU partitioning application. The CPU partition application enables two CPUs to run the system separately, and has the following advantages:
The PFR technology mainly relies on complex logic, and the PFR circuit signal integrity risk is high. These characteristics greatly increase the difficulty of development, production and maintenance. Existing servers may only remotely debug the CPU through the cluster communication port (COM) port or the BMC.
Considering the technical problem in the Background, for the new CPU design (the integration of CPU Southbridge chip and the CPU results in the removal of low-speed interfaces such as the USB, and the CPU partitioning application enables two CPUs to run the operating system separately), since the new generation of CPUs no longer have USB interfaces, the two CPUs (CPU0, CPU1) of the server each have two PCIe buses connected to the new server management system. The gating switch 3 uniformly controls a total of four channels of PCIe buses of the two CPUs. The gating switch 3 may connect two PCIe buses of the currently operating CPU to the baseboard management control apparatus 1 and the USB controller respectively.
When the CPU0 is operating, the gating switch 3 may connect the two PCIe buses of the CPU0 to the baseboard management control apparatus 1 and the USB controller respectively. The CPU may send the PCIe signal through the PCIe bus connected to the baseboard management control apparatus 1. For example, it may send data related to the operating system interface, so that the baseboard management control apparatus 1 may perform display control of the operating system interface, and the USB controller 2 connected to the first USB interface 4 may perform mutual conversion between the USB signal and the PCIe signal. In this way, the first USB interface 4 may perform USB communication with the CPU connected to the gating switch 3 through the USB controller 2.
In order to realize the keyboard and mouse functions of the server, the signals of the keyboard and mouse devices may be sent to the baseboard management control apparatus 1 through the first USB interface 4. After processing the keyboard and mouse instructions, the baseboard management control apparatus 1 may send the keyboard and mouse instructions to the CPU connected to gating switch 3 through the USB controller 2 and the gating switch 3, so as to realize the keyboard and mouse application.
In some embodiments, the baseboard management control apparatus 1 may also assist the CPU connected to the gating switch 3 in startup, which includes providing a verified startup program for the CPU during the startup phase of the server, and receiving startup information sent by the CPU.
Due to the presence of the gating switch 3, the server management system in some embodiments of the present application may also be compatible with existing CPUs, and has strong compatibility and versatility.
Some embodiments of the present application provide a server management system. The server management system may assist two CPUs in startup, and may receive the PCIe signals sent by two CPUs for the display of the operating system interface. It may also send the received keyboard and mouse commands to the CPU connected to the gating switch through the USB controller, so as to realize the keyboard and mouse application. When the USB controller performs mutual conversion between the USB signal and the PCIe signal, the communication between the CPUs connected to the gating switch may be implemented through the first USB interface. The server management system may be applied to a future solution of the CPU partitioning applications without the USB interface, and has a simple structure and strong stability.
In order to better introduce the embodiments of the present application, please refer to
The composition of the BMC, the control module and the trusted root security management module has the advantages of simple structure, low cost and strong stability.
Of course, in addition to the above composition, the baseboard management control apparatus 1 may also be of other compositions.
Considering the existing 2-way server, the CPU0 transmits UART information to the BMC through the ESPI bus and outputs it through the COM interface of the BMC. The ESPI bus speed is high, and the UART bus speed is low. Transmitting UART information by the ESPI greatly reduces the utilization of the ESPI bus. The new server management system has been improved to support the CPU partitioning application. The ESPI mainly runs CPU startup information to improve the efficiency of CPU startup. Since the BMC chip only supports one ESPI interface, in the present application, the ESPI of one of the CPUs (CPU0) may be connected to the ESPI interface of BMC to participate in the startup of the CPU0, and the ESPI of the CPU1 may be connected to the control module to participate in the independent startup of the CPU1 through the control module.
In addition, the control module may also control the state of the gating switch 3. The control module may control the state of the gating switch 3 based on the instruction sent by the BMC.
In some embodiments, the control module is also connected to the LVDS interface of the mainboard.
The control module is also configured for decoupling a low-voltage differential signaling (LVDS) signal coupled from a plurality of designated types of low-speed signals sent by the mainboard and sending it to the BMC, and decoupling an LVDS signal coupled from a plurality of specified types of low-speed signals sent by the BMC and sending it to the mainland.
Due to the introduction of the PCIe bus and ESPI bus of the CPU, the interface between the BMC and the mainboard is inevitably tense. Some low-speed signals, such as I2C. UART and GPIO signals, between the BMC and the mainboard may be logically coupled to the LVDS bus for transmission, and then decoupled through the control module on the mainboard side. Thus, the information interaction between the BMC module and the mainboard is completed by the LVDS bus, which may improve the signal transmission rate and reduce the number of signals for the BMC-mainboard interface.
In some embodiments, the server management system further includes:
The BMC is further configured for outputting the UART signal received from the control module through the UART interface and sending the UART signal sent by the protocol conversion apparatus to the control module.
In the server management system of some embodiments of the present application, the UART signal logically decoupled from the control module is output through the UART interface of the BMC, connected to the second USB interface through the protocol conversion apparatus (UART-to-USB chip, USB UART BRIDGE in
In some embodiments, the control module is also connected to an I3C interface of the CPU.
The control module is configured for:
In order to enable the BMC to debug the CPU through the I3C signal, the control module is also connected to the I3C interface of the CPU, and the control module may connect the I3C signal of the CPU to the BMC, so that the BMC may debug the CPU through the I3C signal.
In addition, it is worth mentioning that the 13C signal of the CPU may also be directly connected to the second USB interface (in this case, the second USB interface may be a TYPEC connector). The serial port information may be debugged through the TYPEC interface, and the CPU may also be debugged through the 13C signal, which improve testing efficiency.
In some embodiments, the gating switch 3 includes:
In some embodiments of the present application, the gating switch 3 includes two 1-out-of-2 PCIe switches and one 2-out-of-2 logic switch, which has a simple structure and low cost.
Of course, the gating switch 3 may also be of other structures.
In some embodiments, the server management system further includes a third USB interface connected to the USB controller 2.
The USB controller 2 is configured for performing mutual conversion between the USB signal and the PCIe signal, so as to achieve communication between the CPU connected to the gating switch 3 and the first USB interface 4 and the third USB interface respectively.
Considering that in addition to the keyboard and mouse, the server is also required to connect to more USB devices. Therefore, a plurality of USB interfaces may be provided. The first USB interface 4 may be an interface of USB2.0 protocol, and the third USB interface May be an interface of USB3.0 or higher protocol, so as to improve user experience.
In some embodiments, the control module is an FPGA.
The FPGA has the advantages of small size, high performance and low cost.
Of course, in addition to the FPGA, the control module may also be of other types.
In some embodiments, the trusted root security management apparatus includes:
Cerberus is an ARM processing-based trusted root security management module, provides multiple SPI interfaces externally, and may complete the check and recovery of the CPU, the BMC and other chips during the power-on phase of the server. The Cerberus solution avoids the stacking of logic switches in the PFR solution and reduces the difficulty of PCB design, and also greatly reduces the difficulty of logic development and improves production efficiency.
Of course, in addition to the above structure, the trust root security management apparatus may also be of other types.
In some embodiments, the present application also provides a server including the server management system in the above embodiments.
For an introduction to the server provided in some embodiments of the present application, please refer to the above embodiments of the server management system.
Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment may be referred to each other. It should also be noted that relational terms herein such as first and second, etc., are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply there is any such relationship or order between these entities or operations. Furthermore, the terms “including”. “comprising” or any variations thereof are intended to embrace a non-exclusive inclusion, such that a process, method, article, or terminal device including a plurality of elements includes not only those elements but also includes other elements not expressly listed, or also includes elements inherent to such a process, method, article, or device. In the absence of further limitation, an element defined by the phrase “including a . . . ” does not exclude the presence of additional identical element in the process, method, article, or terminal device.
The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the present application will not be limited to the embodiments shown herein, but is to conform to the widest scope consistent with the principles and novel features disclosed herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210466930.0 | Apr 2022 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2023/091301 | 4/27/2023 | WO |
