The present invention relates to a servo control circuit which can be manufactured by a CMOS manufacturing process.
A servo control circuit is a circuit for controlling a servo motor to, e.g., adjust the projection angle of an automobile headlight.
The above prior art has the drawback that it employs bipolar transistors, and thus it can not be manufactured by a CMOS manufacturing process.
In view of the foregoing, it is desirous, and thus an objective of the present invention, to provide a servo control circuit which can be manufactured by a CMOS manufacturing process.
In accordance with the foregoing and other objectives, the present invention proposes a servo control circuit which comprises: a first node for receiving a control voltage; a second node for receiving a feedback voltage; an operational amplifier controlling a current on a path according to the voltages at the first and second nodes, the path including an internal voltage node thereon; an analog to digital converter (ADC) for converting the voltage at the internal voltage node to a digital signal; and a control logic circuit for generating a servo control signal according to the digital signal.
From an aspect of the present invention, the proposed servo control circuit superimposes a first multiple (α) of the difference between the control voltage and the feedback voltage (ΔV) to a second multiple (β) of a supply voltage (VCC), so that the voltage at the internal voltage node becomes β(VCC)−α*ΔV. In a preferred embodiment, β=½.
These and other features, aspects, and advantages of the present invention will become better understood with reference to the following description, appended claims, and accompanying drawings.
Referring to
More specifically, when the operational amplifier 116 is at a balanced status, its two inputs should be equal to each other, i.e., V7 (the voltage at the first node)=V8 (the voltage at the second node):
V7=[(R3+R5)/(R1+R3+R5)]*(I1*R1)+Vref*[R1/(R1+R3+R5)]
V8=V7=[(R4+R6)/(R2+R4+R6)]*(IM2*R2)+Vfb*[R2/(R2+R4+R6)]
Wherein IM2=I2+IR9.
For simplicity of calculation, the resistances of the resistors and the current amounts of the current sources can be set such that
R1=R2; R3=R4; R5=R6; I1=I2; thus,
IR9=(Vref−Vfb)/(R3+R5)
Furthermore, the external reference voltage node A is a node in a voltage divider circuit in connection with the supply voltage VCC. From the current in and currents out from the node A, the following equation can be obtained:
[(VCC−VA)/R7]−IR9=VA/R8
wherein VA is the voltage at the node A, and thus
VA=[(R7*R8)/(R7+R8)]*[(VCC/R7)−IR9]
By setting R7=R8:
VA=(VCC/2)−(R7/2)*IR9
And the voltage VB at the node B is thus:
In the last equation, {[(R7/2)+R9]/(R3+R5)} can be taken as a constant α, and the equation can be simplified as VB=(VCC/2)−α*(Vref−Vfb); the meaning of the equation is to multiply the difference ΔV between the voltage Vref and the feedback Vfb by (−α), and the product is superimposed on the voltage (VCC/2).
The voltage VB at the node B is converted to a digital signal by the analog to digital converter 117, and the digital signal is sent to the control logic circuit 118 to control the motor 20. The analog to digital converter 117 need not be a converter of complete levels; it only need be able to distinguish between certain critical levels and convert the signals correspondingly. For example, as shown in
VR1=(VCC/2)+(2%)*VCC
VR2=(VCC/2)+(0.4%)*VCC
VR3=(VCC/2)−(0.4%)*VCC
VR4=(VCC/2)−(2%)*VCC
Of course, other arrangements or other number of levels are also workable.
The meaning of the above arrangement may be better understood with reference to
The voltage VB need not be balanced at the position of (VCC/2); the balance point can be adjusted by the relationship between R7 and R8. As a more general equation, the voltage VB at the node B is equal to β(VCC)−α*ΔV, and β=½ when R7=R8.
The spirit of the present invention has been explained in the foregoing with reference to its preferred embodiments, but it should be noted that the above is only for illustrative purpose, to help those skilled in this art to understand the present invention, and not for limiting the scope of the present invention. Within the same spirit, various modifications and variations can be made by those skilled in this art. For example, the resistances of several resistors are made equal to each other for simplicity of calculation, but they can be arranged otherwise without departing from the spirit of the present invention. The transistors M1 and M2 can be replaced by NMOS transistors, with corresponding modifications (such as the inputs of the operational amplifier 116) to the circuit. The comparators 111-114 may be replaced by a hysteretic comparators. Additional devices may be interposed between any two devices shown in the drawing, without affecting the primary function of the circuit. In view of the foregoing, it is intended that the present invention cover all such modifications and variations, which should interpreted to fall within the scope of the following claims and their equivalents.
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4335321 | Lyons et al. | Jun 1982 | A |
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Number | Date | Country | |
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20090195207 A1 | Aug 2009 | US |