This application is related to co-pending U.S. patent application titled “SETTING AN OPERATING BIAS CURRENT FOR A MAGNETORESISTIVE HEAD USING RATIO OF TARGET VOLTAGE AND MEASURED VOLTAGE”, Ser. No. 11/761,224, filed on the same day as the present application and incorporated herein by reference.
1. Field
The present invention relates to magnetoresistive heads. In particular, the present invention relates to setting an operating bias current for a magnetoresistive head by computing a target operating voltage.
2. Description of the Related Art
Magnetoresistive (MR) heads are typically employed in data storage devices, such as magnetic tape drives and disk drives, for transducing the magnetic transitions recorded on a magnetic medium into a read signal that is demodulated by a read channel. A MR head comprises an MR element having a resistance that varies in response to the magnetic field emanating from the recording medium. The read signal may be generated by applying a constant bias voltage to the MR element and measuring the change in current flowing through the MR element as the resistance varies. Alternatively, the read signal may be generated by applying a constant bias current to the MR element and measuring the change in voltage across the MR element as the resistance varies.
Increasing the bias current of the MR element typically increases the quality of the read signal (increases signal-to-noise); however, setting the bias current too high reduces the lifetime of the MR element. For example, setting the bias current too high can reduce the lifetime of a giant MR element (GMR) due to self-heating and concomitant high current density, and it can reduce the lifetime of a tunneling MR element (TMR) due to dielectric breakdown. The lifetime of the MR element is also typically affected by other operating characteristics, such as the ambient temperature. The prior art has suggested to characterize the MR element using various lifetime testing procedures which applies stresses in order to accelerate the time to failure (e.g., increasing the bias current). The lifetime information is then used to select a nominal bias current setting (taking into account tolerance) for a family of MR elements employed in the field, such as in a family of disk drives. The prior art has also suggested to correlate the bias current settings with MR resistance and ambient temperature during the lifetime testing, and to use this information to adjust the bias current setting while in the field.
Certain MR elements, such as tunneling MR elements, exhibit a negative voltage coefficient of resistance resulting in a non-linear voltage drop at higher current densities as illustrated in
There is, therefore, a need for an efficient technique to set an operating bias current for an MR element.
An embodiment of the present invention comprises a disk drive having a disk, and a head actuated over the disk, the head comprising a magnetoresistive (MR) element. Control circuitry within the disk drive sets an operating bias current for the MR element by computing a target voltage for the MR element, applying a bias current to the MR element, measuring a voltage across the MR element corresponding to the bias current, and adjusting the bias current applied to the MR element until the measured voltage substantially equals the target voltage.
In one embodiment, the control circuitry is further operable to set the operating bias current for the MR element by computing a resistance estimate for the MR element, and computing the target voltage in response to the resistance estimate.
In another embodiment, the control circuitry is further operable to set the operating bias current for the MR element by measuring an ambient temperature of the MR element, and computing the target voltage in response to the measured ambient temperature.
In still another embodiment, the disk drive comprises a heater for heating the MR element in order to adjust a fly-height of the MR element, wherein the control circuitry computes the target voltage in response to a parameter setting for the heater. In one embodiment, the parameter setting comprises at least one of a heater current, a heater voltage, and a heater power. In another embodiment, the control circuitry computes the target voltage according to:
b0+(b1·R)+(b2·W)+(b3·R·W)+(b4·Ftemp)+(b5·Ftemp·R)
where:
R is a resistance estimate for the MR element;
Ftemp is a measured ambient temperature of the MR element;
W is the heater power; and
b0-b5 are coefficients.
In yet another embodiment, the control circuitry computes the target voltage using a function comprising a DC offset. The control circuitry determines a first DC offset of the function corresponding to a first ambient temperature, determines a second DC offset of the function corresponding to a second ambient temperature, measures an ambient temperature of the disk drive, and adjusts the DC offset of the function in response to the first DC offset, the second DC offset, and the measured ambient temperature. In one embodiment, the control circuitry adjusts the target voltage in response to the adjusted DC offset, and adjusts the bias current applied to the MR element until the measured voltage substantially equals the adjusted target voltage.
Another embodiment of the present invention comprises a disk drive having a disk, and a head actuated over the disk, the head comprising a magnetoresistive (MR) element. A heater heats the MR element in order to adjust a fly-height of the MR element, and control circuitry sets an operating bias current for the MR element in response to a parameter setting of the heater.
Another embodiment of the present invention comprises a method of setting an operating bias current for a magnetoresistive (MR) element of a disk drive, the disk drive comprising a disk, and a head actuated over the disk, wherein the head comprises the MR element. A target voltage for the MR element is computed, a bias current is applied to the MR element, a voltage across the MR element is measured corresponding to the bias current, and the bias current applied to the MR element is adjusted until the measured voltage substantially equals the target voltage.
In the embodiment of
In one embodiment, a target voltage is computed and a corresponding bias current is determined for each MR element (e.g., for each head in each individual disk drive).
The flow diagram of
At step 48 the flow diagram of
The target voltage may be adjusted in response to any suitable parameter that affects the longevity of the MR element. In one embodiment, an ambient temperature of the MR element is measured and the target voltage is adjusted in response to the ambient temperature. In one embodiment, a single ambient temperature measurement is taken for the disk drive, and in an alternative embodiment, an ambient temperature measurement is taken for each head in the disk drive. In another embodiment, the MR element is heated to adjust a fly-height of the MR element, and the target voltage is adjusted in response to one or more characteristics of the heating process, such as the heating power, the heating voltage, and/or the heating current. In other embodiments, the target voltage may be adjusted in response to a write current applied to a write coil of the head, the magnitude of the bias current applied to the MR element, and/or a detected altitude of the MR element.
In addition, the target voltage may be adjusted using any suitable algorithm in response to the parameters that affect the longevity of the MR element. For example, in one embodiment the target voltage is adjusted according to:
b0+(b1·R)+(b2·W)+(b3·R·W)+(b4·Ftemp)+(b5·Ftemp·R)
where:
R is a resistance estimate for the MR element;
Ftemp is an ambient temperature of the MR element;
W is the heating power; and
b0-b5 are coefficients.
In one embodiment, the coefficients b0-b5 are determined using any well known testing techniques for determining time-to-failure of a typical MR element. For example, a number of MR elements may be tested by adjusting the above parameters (ambient temperature, heating power, resistance) and determining the coefficients bO-b5 for the above equation that provides the best estimate of the maximum target voltage (from a lifetime perspective) using any suitable curve fitting technique.
In one embodiment, the coefficient b0 in the above equation (which represents a DC offset for the target voltage) is adjusted to obtain an optimal target voltage that minimizes a bit error rate of the disk drive, as well as compensates for temperature changes. In one embodiment, a nominal temperature coefficient b0
The nominal and hot coefficients (b0
Ft
After determining the adjusted coefficient b0′ corresponding to the current temperature Ftemp, at step 88 a corresponding optimal voltage Vopt is computed using the above equation. The flow diagram of
Using an equation based technique for determining the target operating voltage for the MR element as a function of certain parameters (e.g., resistance, and/or temperature, etc.), and then determining the corresponding bias current (e.g., using the flow diagram of
Any suitable control circuitry 6 may be employed in the embodiments of the present invention, such as any suitable integrated circuit or circuits. For example, the control circuitry 6 may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain steps described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or “system on a chip” (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into an SOC, wherein the preamp circuit comprises suitable circuitry for generating and applying the bias current to the MR element and for measuring the voltage across the MR element.
In one embodiment, the control circuitry 6 comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the steps of the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a system on a chip (SOC). In another embodiment, the instructions are stored on the disk 2 and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry 6 comprises suitable logic circuitry, such as state machine circuitry.
Any suitable MR element may be employed in the embodiments of the present invention, including giant MR elements (GMR), spin-valve MR elements (SVMR), tunneling MR elements (TMR), and current-perpendicular-to-plane MR elements (CPPMR).
Number | Name | Date | Kind |
---|---|---|---|
3879674 | Dragon | Apr 1975 | A |
4914398 | Jove et al. | Apr 1990 | A |
5283521 | Ottesen et al. | Feb 1994 | A |
5412518 | Christner et al. | May 1995 | A |
5418660 | Sato et al. | May 1995 | A |
5420513 | Kimura | May 1995 | A |
5790334 | Cunningham | Aug 1998 | A |
5978163 | Cunningham | Nov 1999 | A |
6111715 | Tsuchiya et al. | Aug 2000 | A |
6115201 | Enarson et al. | Sep 2000 | A |
6151177 | Shrinkle et al. | Nov 2000 | A |
6169638 | Morling | Jan 2001 | B1 |
6195219 | Smith | Feb 2001 | B1 |
6262572 | Franco et al. | Jul 2001 | B1 |
6262858 | Sugiyama et al. | Jul 2001 | B1 |
6288863 | Flinsbaugh | Sep 2001 | B1 |
6320713 | Tretter et al. | Nov 2001 | B1 |
6341046 | Peterson | Jan 2002 | B1 |
6452735 | Egan et al. | Sep 2002 | B1 |
6473257 | Shimazawa et al. | Oct 2002 | B1 |
6483676 | Nakatani | Nov 2002 | B2 |
6512647 | Quak et al. | Jan 2003 | B1 |
6512648 | Tsuchiya et al. | Jan 2003 | B1 |
6574061 | Ling et al. | Jun 2003 | B1 |
6603340 | Tachimori | Aug 2003 | B2 |
6654191 | Ottesen et al. | Nov 2003 | B2 |
6731448 | Briskin et al. | May 2004 | B2 |
6751039 | Ngo et al. | Jun 2004 | B1 |
6762914 | Fox et al. | Jul 2004 | B2 |
6801376 | Smith | Oct 2004 | B2 |
6903889 | Li et al. | Jun 2005 | B2 |
7097110 | Sheperek et al. | Aug 2006 | B2 |
7130143 | Tretter | Oct 2006 | B1 |
7265577 | Madurawe | Sep 2007 | B2 |
7480115 | Hiroyuki et al. | Jan 2009 | B2 |
7804657 | Hogg et al. | Sep 2010 | B1 |
20030169528 | Lim et al. | Sep 2003 | A1 |
20060119963 | Hidaka | Jun 2006 | A1 |
20070297819 | Hagiwara et al. | Dec 2007 | A1 |
20080100948 | Tretter | May 2008 | A1 |