Claims
- 1. A memory cell comprising:
- two cross-coupled inverters each including a p-channel transistor and an n-channel transistor, said p and n channel transistors in a respective inverter sharing a common gate, each inverter further including a first diode connected to and between the n-channel transistor and the p-channel transistor;
- second diodes connected between and to the gate of one inverter and a drain of a selected transistor of the other inverter, wherein the gate common to said p and n channel transistors of an inverter also overlies said first and second diodes, and wherein each second diode connects to the drain of said n-channel transistor; and
- coupling transistors each connected to an anode of said second diode and the drain of the p-channel transistor.
- 2. A memory cell as recited in claim 1 wherein said coupling transistors are p-channel transistors.
- 3. A memory cell comprising two cross-coupled inverters each including a pull-up element and a pull-down element, a first diode connected to and between said pull-up and pull-down elements, the cross-coupling accomplished through the connection of second diodes across associated inputs of one inverter and the pull-down element of another inverter, said cross-coupling being further accomplished through the connection of coupling transistors across associated inputs of one inverter and the pull-up element of another inverter.
- 4. A memory cell as recited in claim 3 wherein the input to one inverter is capacitively coupled to said first diode of the other inverter.
Parent Case Info
This application is a Continuation of application Ser. No. 288,541, filed Dec. 21, 1988, now abandoned.
Government Interests
This invention was made with Government support under contract number F29601-86-C-0020.
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Kind |
4660177 |
O'Connor |
Apr 1987 |
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4724530 |
Dingwall |
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4760557 |
Stewart et al. |
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Continuations (1)
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Number |
Date |
Country |
Parent |
288541 |
Dec 1988 |
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