Shading compensation circuit and control method thereof

Abstract

A shading compensation circuit is provided which is capable of storing correction coefficients for shading compensation having optimal bit lengths, so that the data size of the correction coefficients can be reduced. The shading compensation circuit 10 for correcting the shading properties with respect to a horizontal direction and a vertical direction, has horizontal correction coefficient HHK and vertical correction coefficient VHK each having a bit length optimized according to a horizontal direction counter value HCT or a vertical direction counter value VCT. The horizontal and vertical correction coefficients HHK, VHK for the periphery of the image data are longer in bit length than the correction coefficients HHK, VHK for the center of the image data.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the structure of a shading compensation circuit constructed according to an embodiment;

FIG. 2 is an explanatory diagram showing the contents of a correction coefficient RAM;

FIG. 3 is an explanatory diagram showing the contents of a register;

FIG. 4 is a flow chart of an operation of a first address generation unit;

FIG. 5 is a flow chart of an operation of the first address generation unit;

FIG. 6 is a flow chart of an operation of a second address generation unit;

FIG. 7 is a flow chart of an operation of the second address generation unit;

FIG. 8 is a block diagram showing the configuration of a first correction coefficient acquisition unit;

FIG. 9 is a flow chart of an operation of the first correction coefficient acquisition unit;

FIG. 10 is a flow chart of an operation of the first correction coefficient acquisition unit;

FIG. 11 is a block diagram showing the configuration of a second correction coefficient acquisition unit;

FIG. 12 is a flow chart of an operation of the second correction coefficient acquisition unit;

FIG. 13 is a flow chart of an operation of the second correction coefficient acquisition unit;

FIG. 14 is a timing chart of an operation of the shading compensation circuit;

FIG. 15 is a timing chart of the operation of the shading compensation circuit;

FIG. 16 is an explanatory diagram showing the relationship between image data and correction coefficients; and

FIG. 17 is a block diagram showing the configuration of a prior art shading compensation circuit.

Claims

1. A shading compensation circuit for performing shading compensation on image data the pixels of which are arranged in a horizontal direction and a vertical direction perpendicular to the horizontal direction, such that shading properties with respect to either the horizontal or vertical direction are corrected, wherein correction coefficients each having a specified bit length are stored according to pixel positions, andwherein the correction coefficients for the periphery of the image data are longer in bit length than the correction coefficients for the center of the image data.

2. The shading compensation circuit according to claim 1, comprising: a storage unit for storing the correction coefficients for successive data pieces the boundaries of which are interlinked.

3. The shading compensation circuit according to claim 2, comprising: an address generation unit for generating an address of the storage unit based on the cumulative sum of the numbers of bits of the correction coefficients informed by bit-number information.

4. The shading compensation circuit according to claim 2, comprising: a low-order shift register for retaining read-out data from the storage unit; anda high-order shift register coupled to the high-order side of the low-order shift register,wherein after the read-out data from the storage unit is retained by the low-order shift register, the contents of data retained by the low-order shift register and high-order shift register are linked and shifted to the high-order side by the number of bits of the correction coefficients informed by bit-number information and data stored in the high-order shift register is output.

5. The shading compensation circuit according to claim 1, wherein the correction coefficients are allocated for a plurality of areas divided in the horizontal direction or the vertical direction such that the correction coefficients for the areas in the periphery of the image data are longer in bit length than the correction coefficients for the areas at the center of the image data.

6. The shading compensation circuit according to claim 5, comprising: a boundary information storage unit for storing area boundary information indicative of the boundaries of the areas;a look-up information storage unit for storing bit number look-up information indicative of the relationship between the areas and the bit lengths of the correction coefficients;an area judgment unit for making a judgment to determine an area to which a specified pixel belongs, referring to the boundary information storage unit; anda look-up unit for obtaining the bit-number information from the result of the judgment of the area judgment unit and the bit-number look-up information.

7. A method of controlling a shading compensation circuit for performing shading compensation on image data the pixels of which are arranged in a horizontal direction and a vertical direction perpendicular to the horizontal direction, such that shading properties with respect to either the horizontal or vertical direction are corrected, the method comprising the steps of:determining correction coefficients having a specified bit length according to a pixel position; andperforming shading compensation based on the correction coefficients,wherein the correction coefficients for the periphery of the image data are longer than the correction coefficients for the center of the image data.

8. The method of controlling a shading compensation circuit according to claim 7, the shading compensation circuit having a storage unit, the method further comprising the step of: storing, in the storage unit, the correction coefficients for successive data pieces the boundaries of which are interlinked.

9. The method of controlling a shading compensation circuit according to claim 8, the method further comprising the step of: generating an address of the storage unit based on the cumulative sum of the numbers of bits of the correction coefficients informed by bit-number information.

10. The method of controlling a shading compensation circuit according to claim 8, the shading compensation circuit having a low-order shift register for retaining read-out data from the storage unit and a high-order shift register coupled to the high-order side of the low-order shift register, the method further comprising the steps of: retaining read-out data from the storage unit by the low-order shift register;linking the contents of the low-order shift register and the contents of the high-order shift register and shifting them to the high-order side by the number of bits of the correction coefficients informed by the bit-number information; andoutputting data stored in the high-order shift register.

11. The method of controlling a shading compensation circuit according to claim 7, wherein the correction coefficients are allocated for a plurality of areas divided in the horizontal direction or the vertical direction such that the correction coefficients for the areas in the periphery of the image data are longer in bit length than the correction coefficients for the areas at the center of the image data.

12. The method of controlling a shading compensation circuit according to claim 11, the shading compensation circuit having a boundary information storage unit for storing area boundary information indicative of the boundaries of the areas and a look-up information storage unit for storing bit number look-up information indicative of the relationship between the areas and the bit lengths of the correction coefficients, the method further comprising the steps of:making a judgment to determine an area to which a specified pixel belongs, referring to the boundary information storage unit; andobtaining bit-number information from the result of the judgment made in the step of making a judgment and the bit-number look-up information.