Patent Application
20240074158
Embodiments of the disclosure relate generally to memory systems and, more specifically, to memory devices and formation thereof.
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data, and includes random-access memory (RAM), dynamic random-access memory (DRAM), static RAM (SRAM), or synchronous dynamic random-access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory, such as phase-change random-access memory (PCRAM), resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), or three-dimensional (3D) XPoint™ memory, among others. Properties of memory devices can be improved by enhancements to the design and fabrication of components of the memory devices.
The drawings, which are not necessarily drawn to scale, illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
The following detailed description refers to the accompanying drawings that show, by way of illustration, various embodiments that can be implemented. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice these and other embodiments. Other embodiments may be utilized, and structural, logical, mechanical, and electrical changes may be made to these embodiments. The term “horizontal” as used in this application is defined as a plane parallel to a conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Various features can have a vertical component to the direction of their structure. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. The following detailed description is, therefore, not to be taken in a limiting sense.
In DRAM processing, an effective starting configuration for fabricating conductive paths between capacitors of memory cells, active devices of the memory cells to access the capacitors, and data lines (e.g., bit lines) for the memory cells can include an interlayer dielectric (ILD) on shallow trench isolation (STI) regions about material for active areas, where the active areas are active areas of the active devices of the memory cells. STI regions are dielectric regions that separate active devices in an integrated circuit. The active devices can be transistors such as, but not limited to, metal-oxide-semiconductor (MOS) transistors or variations thereof. The ILD can be structured as multiple dielectric layers having different compositions and thickness selected according to the techniques for processing the conductive paths and associated structures. Ideally, the ILD is situated on tops of the STI regions and tops of the material for active areas that are at the same level, where exposing the material for active areas, to form contacts, would use a minimum over etch at the last etch of the ILD. However, the material for active areas between STIs tends to be rounded or tapered at the top of the material for active areas with material effectively from the ILD on top of the material for active areas extending to a bottom level of the ILD that is at the level of the top to the STI regions. Typically, to clear out this material on top of the material for active areas and expose the top of the material for active areas for further processing, an over etch significantly deeper into STI than the ideal case is conducted. Such processing can lead to creating a deep, large critical dimension (CD) metal region at the upper portion of the STI region, which can cause shorts at downstream processing of cell contacts for capacitors.
In various embodiments, shorting between a cell contact to a capacitor of a memory array of a memory device and a data line contact to a data line of the memory device can be avoided by STI recess control. STI recess control can include processing using a dielectric liner in which a dielectric corner from the dielectric liner remains after substantial removal of the dielectric liner, where the dielectric corner provides electrical isolation in contrast to procedures in which corners generated from STI recess are metal corners. The processing can include selective etching and corner liner fill. The selective etching process can include, but is not limited to, one or more dry etching procedures. The use of the dielectric liner in processing allows for control of data line contacts and STI recess. STI recess control can include application of a selective etch at the last layer of the ILD above the material for the active areas. With the material for an active area being a silicon region, the STI region being a dielectric nitride region, and the ILD having an oxide on the tops of the STI region and tops of the silicon region, the selective etch can include an oxide etch step in which oxide is etched with high selectivity to silicon but low selectivity to nitrogen rather than using an oxide etch with relatively low selectivity to both silicon and nitrogen. This etch selectivity allows for the removal of oxide and nitrogen as deep as appropriate, while leaving the silicon conductive region unetched.
The silicon region for an active area can be exposed for downstream processing as desired, regardless of its shape at the effective starting configuration of the ILD above the silicon region. The selective etching provides an opening that can be filled with dielectric liner. The dielectric liner can be formed by filling the opening with an atomic layer deposition (ALD) of a dielectric material. ALD is a monolayer by monolayer deposition techniques that can allow fabrication of thin layers of a number of monolayers to several nanometers of material and larger thickness of materials. ALD allows pinch off at the corner of the silicon region for the active area and the nitrogen STI region. The dielectric formed by ALD can be a non-oxide dielectric material. For example, the non-oxide dielectric material can be, but is not limited to, a dielectric nitride or silicon carbide. An isotropic removal of the dielectric material of the liner can be conducted, leaving a portion of the dielectric that filled the corner of the silicon conductive region with the nitride STI, while clearing out sacrificial sidewall portions of the dielectric liner and portions of the dielectric liner on top of the silicon of the active area. A wet etch can be conducted to perform the isotropic removal of the dielectric material. The portion of the dielectric liner remaining at the corner can provide electric insulation and prevent shorts at downstream processing.
STI regions can be structured with respect to active regions 120. Processing data line contacts 105 and cell contacts 115 with respect to the STI regions can be conducted to reduce or prevent shorting between data line contacts 105 and adjacent cell contacts 115. For example, a data line contact 105 and an adjacent cell contact 115 between access line 130-1 and access line 130-2 with respect to data lines 110-1 and 110-2 are significantly close to each other, which can make these contacts susceptible to establishment of shorts between data line contacts 105 and adjacent cell contacts 115 during processing of memory device 100. Recess control of STIs associated with data line contact 105 can be implemented to significantly reduce the occurrence of such shorts.
Silicon material for an active area (Si AA) 222-1 can be located between STI 212-1 and STI 212-2. A Si AA 222-2 can be located between STI 212-1 and STI 212-3. A Si AA 222-3 can be located between STI 212-2 and STI 212-4. Though Si AA 222-1, Si AA 222-2, and Si AA 222-3 are shown with rounded shapes, such material for active areas can be formed with ends that are tapered at the top of the material or have other shapes. Si AA 222-1, Si AA 222-2, and Si AA 222-3 can be formed with the formation of access devices that have been previously formed below ILD 206. Si AA 222-1, Si AA 222-2, and Si AA 222-3 are separated from dielectric region 207 by dielectrics 211. Dielectrics 211 can be formed at the time of formation of dielectric region 207 with material of dielectric region 207, though dielectrics 211 and the rounded or tapered ends of Si AA 222-1, Si AA 222-2, and Si AA 222-3 are not ideal. Subsequent processing, as taught herein, can mitigate the formation of dielectrics 211 along with providing electrical isolations between contact components.
Various deposition techniques for components of structures 200-900 in the process flow of
Each memory cell 1125 can include a single transistor 1127 and a single capacitor 1129, which is commonly referred to as a 1T1C (one-transistor-one capacitor cell). One plate of capacitor 1129, which can be termed the “node plate,” is connected to the drain terminal of transistor 1127, whereas the other plate of the capacitor 1129 is connected to ground 1124. Each capacitor 1129 within the array of 1T1C memory cells 1125 typically serves to store one bit of data, and the respective transistor 1127 serves as an access device to write to or read from storage capacitor 1129.
The transistor gate terminals within each row of rows 1154-1, 1154-2, 1154-3, and 1154-4 are portions of respective access lines 1130-1, 1130-2, 1130-3, and 1130-4 (for example, word lines), and the transistor source terminals within each of columns 1156-1, 1156-2, 1156-3, and 1156-4 are electrically connected to respective data lines 1110-1, 1110-2, 1110-3, and 1110-4 (for example bit lines). The connection of a data line, such as data line 1110-2, to a memory cell, such as dotted memory cell 1125, can be made using a data line contact 1105. Data line contact 1105 can be structured similar to data line contact 105 of
A row decoder 1132 can selectively drive the individual access lines 1130-1, 1130-2, 1130-3, and 1130-4, responsive to row address signals 1131 input to row decoder 1132. Driving a given access line at a high voltage causes the access transistors within the respective row to conduct, thereby connecting the storage capacitors within the row to the respective data lines, such that charge can be transferred between the data lines and the storage capacitors for read or write operations. Both read and write operations can be performed via sense amplifier circuitry 1140, which can transfer bit values between the memory cells 1125 of the selected row of the rows 1154-1, 1154-2, 1154-3, and 1154-4 and input/output buffers 1146 (for write/read operations) or external input/output data buses 1148.
A column decoder 1142 responsive to column address signals 1141 can select which of the memory cells 1125 within the selected row is read out or written to. Alternatively, for read operations, the storage capacitors 1129 within the selected row may be read out simultaneously and latched, and the column decoder 1142 can then select which latch bits to connect to the output data bus 1148. Since read-out of the storage capacitors destroys the stored information, the read operation is accompanied by a simultaneous rewrite of the capacitor charge. Further, in between read/write operations, the capacitor charge is repeatedly refreshed to prevent data loss. Details of read/rewrite, write, and refresh operations are well-known to those of ordinary skill in the art.
DRAM device 1100 may be implemented as an integrated circuit within a package that includes pins for receiving supply voltages (e.g., to provide the source and gate voltages for the transistors 1127) and signals (including data, address, and control signals).
In two-dimensional (2D) DRAM arrays, the rows 1154-1, 1154-2, 1154-3, and 1154-4 and columns 1156-1, 1156-2, 1156-3, and 1156-4 of memory cells 1125 are arranged along a single horizontal plane (i.e., a plane parallel to the layers) of the semiconductor substrate, e.g., in a rectangular lattice with mutually perpendicular horizontal access lines 1130-1, 1130-2, 1130-3, and 1130-4 and data lines 1110-1, 1110-2, 1110-3, and 1110-4. In 3D DRAM arrays, the memory cells 1125 are arranged in a 3D lattice that encompasses multiple vertically stacked horizontal planes corresponding to multiple device tiers of a multi-tier substrate assembly, with each device tier including multiple parallel rows of memory cells 1125 whose transistor gate terminals are connected by horizontal access lines such as access lines 1130-1, 1130-2, 1130-3, and 1130-4. A “device tier,” as used herein, may include multiple layers (or levels) of materials, but forms the components of memory devices of a single horizontal tier of memory cells. Data lines 1110-1, 1110-2, 1110-3, and 1110-4 can extend vertically through all or at least a vertical portion of the multi-tier structure, and each of the data lines 1110-1, 1110-2, 1110-3, and 1110-4 can connect to the transistor source terminals of respective vertical columns 1156-1, 1156-2, 1156-3, and 1156-4 of associated memory cells 1125 at the multiple device tiers. Such a 3D configuration of memory cells enables further increases in bit density compared with 2D arrays.
At 1230, a data line contact is formed contacting the dielectric material and coupled to the conductive region. At 1240, a cell contact to the memory cell is formed contacting the dielectric material, replacing a portion of the dielectric isolation region such that the dielectric material is between the cell contact and the data line contact.
Variations of method 1200 or methods similar to method 1200 can include a number of different embodiments that may be combined depending on the application of such methods and/or the architecture of systems in which such methods are implemented. Such methods can include forming a silicon plug between the data line contact and the conductive region after recessing the conductive region in a procedure to form the data line contact to the conductive region. Variations can include forming a capacitor coupled to the cell contact.
At 1320, a liner of dielectric material is formed in the first opening. The formed liner covers the exposed top of the conductive region and the exposed portion of the shallow trench isolation region. Forming the liner of dielectric material can include forming the liner by atomic layer deposition. The dielectric material can be a non-oxide dielectric. The non-oxide dielectric can include one or more of a dielectric nitride or silicon carbide.
At 1330, portions of the liner are removed while leaving a corner of the dielectric material on the shallow trench isolation regions about the top of the conductive region. At 1340, portions of the conductive region are removed, while maintaining the corner of the dielectric material on the shallow trench isolation region. Removing the portions of the liner can include performing an isotropic removal of the portions of the liner. The isotropic removal can include performing a wet etch of the liner.
At 1350, a data line contact is formed contacting the corner and coupled to a remaining portion of the conductive region after removing the portions of the conductive region. At 1360, a cell contact is formed, where the cell contact is separated from the data line contact by the corner of the dielectric material.
Variations of method 1300 or methods similar to method 1300 can include a number of different embodiments that may be combined depending on the application of such methods and/or the architecture of systems in which such methods are implemented. Such methods can include forming the data line contact by forming a conductive plug contacting the remaining portion of the conductive region and forming the data line contact above and contacting the conductive plug. The conductive plug can be a polysilicon plug and the data line contact can include tungsten. Other materials can be used for the conductive plug and data line contact depending on the materials selected for forming the memory device.
In various embodiments, a memory device can include a memory cell having a storage element and an access device, a data line contact coupled to the access device of the memory cell, and a cell contact coupled to the access device of the memory cell. A shallow trench isolation region is situated adjacent to and contacting the data line contact. A dielectric structure can contact the data line contact and the cell contact, where the dielectric structure is on and contacting the shallow trench isolation region and separates the data line contact from the cell contact.
Variations of such a memory device and its features, as taught herein, can include a number of different embodiments and features that may be combined depending on the application of such memory devices, the format of such memory devices, and/or the architecture in which such memory devices are implemented. Features of such memory devices can include the dielectric structure being a non-oxide dielectric. The non-oxide dielectric can include one or more of a dielectric nitride, silicon carbide, or other materials. Variations can include the data line contact connected to a metallic data line. The metallic data line can be, but is not limited to, tungsten. Variations can include the access device being a transistor and the storage element can be a capacitor.
Electronic devices, such as mobile electronic devices (e.g., smart phones, tablets, etc.), electronic devices for use in automotive applications (e.g., automotive sensors, control units, driver-assistance systems, passenger safety or comfort systems, etc.), and internet-connected appliances or devices (e.g., Internet-of-Things (IoT) devices, etc.), have varying storage needs depending on, among other things, the type of electronic device, use environment, performance expectations, etc. Electronic devices can be broken down into several main components: a processor (e.g., a central processing unit (CPU) or other main processor); memory (e.g., one or more volatile or non-volatile RAM memory device, such as DRAM, mobile or low-power double-data-rate synchronous DRAM (DDR SDRAM), etc.); and a storage device (e.g., non-volatile memory (NVM) device, such as flash memory, ROM, a solid-state drive (SSD), a MultiMediaCard (MMC), or other memory card structure or assembly, etc.). In certain examples, electronic devices can include a user interface (e.g., a display, touch-screen, keyboard, one or more buttons, etc.), a graphics processing unit (GPU), a power management circuit, a baseband processor or one or more transceiver circuits, etc. As used herein, “processor device” means any type of computational circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including a group of processors or multi-core devices.
Examples, as described herein, can include, or can operate by, logic, components, devices, packages, or mechanisms. Circuitry is a collection (e.g., set) of circuits implemented in tangible entities that include hardware (e.g., simple circuits, gates, logic, etc.). Circuitry membership can be flexible over time and underlying hardware variability. Circuitries include members that can, alone or in combination, perform specific tasks when operating. In an example, hardware of the circuitry can be immutably designed to carry out a specific operation (e.g., hardwired). In an example, the hardware of the circuitry can include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including a computer readable medium physically modified (e.g., magnetically, electrically, moveable placement of invariant massed particles, etc.) to store instructions of the specific operation. The instructions enable participating hardware (e.g., the execution units or a loading mechanism) to create members of the circuitry in hardware via the variable connections to carry out portions of the specific tasks when in operation. Accordingly, the computer-readable medium is communicatively coupled to the other components of the circuitry when the device is operating. In an example, any of the physical components can be used in more than one member of more than one circuitry.
The machine 1400 can include a hardware processor 1450 (e.g., a CPU, a GPU, a hardware processor core, or any combination thereof), a main memory 1454, and a static memory 1456, some or all of which can communicate with each other via an interlink 1458 (e.g., bus). Machine 1400 can further include a display device 1460, an input device 1462, which can be an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device 1464 (e.g., a mouse). In an example, display device 1460, input device 1462, and UI navigation device 1464 can be a touch screen display. Machine 1400 can additionally include a mass storage device (e.g., drive unit) 1451, a network interface device 1453, a signal generation device 1468, and one or more sensors 1466, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. Machine 1400 can include an output controller 1469, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).
Machine 1400 can include one or more machine-readable media on which is stored one or more sets of data structures or instructions 1455 (e.g., software, microcode, or other type of instructions) embodying or utilized by machine 1400 to perform any one or more of the techniques or functions for which machine 1400 is designed. The instructions 1455 can reside, completely or at least partially, within main memory 1454, within static memory 1456, or within hardware processor 1450 during execution thereof by machine 1400. In an example, one or any combination of hardware processor 1450, main memory 1454, static memory 1456, or mass storage device 1451 can constitute the machine-readable media on which is stored one or more sets of data structures or instructions. Various ones of hardware processor 1450, main memory 1454, static memory 1456, or mass storage device 1451 can include one or more antifuses using components of a FinFET architecture as discussed herein.
While an example machine-readable medium is illustrated as a single medium, the term “machine-readable medium” can include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store instructions 1455 or data. The term “machine-readable medium” can include any medium that is capable of storing instructions for execution by machine 1400 and that cause machine 1400 to perform any one or more of the techniques to which machine 1400 is designed, or that is capable of storing data structures used by or associated with such instructions. Non-limiting machine-readable medium examples can include solid-state memories, optical media, and magnetic media. Specific examples of non-transitory machine-readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., EPROM, EEPROM) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and compact disc-ROM (CD-ROM) and digital versatile disc-read only memory (DVD-ROM) disks.
Instructions 1455 (e.g., software, programs, an operating system (OS), etc.) or other data stored on mass storage device 1451 can be accessed by main memory 1454 for use by hardware processor 1450. Main memory 1454 (e.g., DRAM) is typically fast, but volatile, and thus a different type of storage than mass storage device 1451 (e.g., an SSD), which is suitable for long-term storage, including while in an “off” condition. Instructions 1455 or data in use by a user or machine 1400 are typically loaded in main memory 1454 for use by hardware processor 1450. When main memory 1454 is full, virtual space from mass storage device 1451 can be allocated to supplement main memory 1454; however, because mass storage device 1451 is typically slower than main memory 1454, and write speeds are typically at least twice as slow as read speeds, use of virtual memory can greatly reduce user experience due to storage device latency (in contrast to main memory 1454, e.g., DRAM). Further, use of mass storage device 1451 for virtual memory can greatly reduce the usable lifespan of mass storage device 1451.
Storage devices optimized for mobile electronic devices, or mobile storage, traditionally include MMC solid-state storage devices (e.g., micro Secure Digital (microSD™) cards, etc.). MMC devices include a number of parallel interfaces (e.g., an 8-bit parallel interface) with a host device and are often removable and separate components from the host device. In contrast, embedded MMC (eMMC™) devices are attached to a circuit board and considered a component of the host device, with read speeds that rival Serial Advanced Technology Attachment (SATA)-based SSD devices. However, demand for mobile device performance continues to increase, such as to fully enable virtual or augmented-reality devices, utilize increasing networks speeds, etc. In response to this demand, storage devices have shifted from parallel to serial communication interfaces. Universal Flash Storage (UFS) devices, including controllers and firmware, communicate with a host device using a low-voltage differential signaling (LVDS) serial interface with dedicated read/write paths, further advancing greater read/write speeds.
Instructions 1455 can further be transmitted or received over a network 1459 using a transmission medium via signal generation device 1468 or network interface device 1453 utilizing any one of a number of transfer protocols (e.g., frame relay, Internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks can include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks (e.g., Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards known as Wi-Fi®, IEEE 802.16 family of standards known as WiMax®), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, among others. In an example, signal generation device 1468 or network interface device 1453 can include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or more antennas to connect to network 1459. In an example, signal generation device 1468 or network interface device 1453 can include a plurality of antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term “transmission medium” shall be taken to include any tangible medium that is capable of carrying instructions to and for execution by machine 1400 or data to or from machine 1400, and can include instrumentalities to propagate digital or analog communications signals to facilitate communication of such instructions, which instructions may be implemented by software or data.
The following are example embodiments of methods and devices, in accordance with the teachings herein.
An example method 1 of forming a memory device can comprise recessing a portion of a dielectric isolation region, creating a corner between the dielectric isolation region and a conductive region, the conductive region being material for an active area of an access device for a memory cell of the memory device; filling the corner with a dielectric material, the dielectric material being different from material of the dielectric isolation region; forming a data line contact contacting the dielectric material and coupled to the conductive region; forming a cell contact to the memory cell contacting the dielectric material, replacing a portion of the dielectric isolation region such that the dielectric material is between the cell contact and the data line contact.
An example method 2 of forming a memory device can include features of example method 1 of forming a memory device and can include filling the corner with the dielectric material to include forming the dielectric material by atomic layer deposition.
An example method 3 can include features of example method 2 of forming a memory device and features of any of the preceding example methods of forming a memory device and can include the dielectric material being a non-oxide dielectric.
An example method 4 of forming a memory device can include features of any of the preceding example methods of forming a memory device and can include forming the data line contact to the conductive region to include forming a silicon plug between the data line contact and the conductive region after recessing the conductive region.
An example method 5 can include features of any of the preceding example methods of forming a memory device and can include forming a capacitor coupled to the cell contact.
In an example method 6 of forming a memory device, any of the example methods 1 to 5 of forming a memory device may be performed to structure an electronic memory apparatus further comprising a host processor and a communication bus extending between the host processor and a memory device.
In an example method 7 of forming a memory device, any of the example methods 1 to 6 of forming a memory device may be modified to include operations set forth in any other of method examples 1 to 6 of forming a memory device.
In an example method 8 of forming a memory device, any of the example methods 1 to 7 of forming a memory device may be implemented at least in part through use of instructions stored as a physical state in one or more machine-readable storage devices.
An example method 9 of forming a memory device can include features of any of the preceding example methods 1 to 8 of forming a memory device and can include performing functions associated with any features of example electronic devices 1 to 8 of forming a memory device.
An example method 10 of forming a memory device can comprise forming a first opening through sacrificial dielectric regions, exposing a top of a conductive region and exposing a portion of a shallow trench isolation region adjacent to and contacting the conductive region, the conductive region being material for an active area of an access device for a memory cell of the memory device; forming a liner of dielectric material in the first opening, covering the exposed top of the conductive region and the exposed portion of the shallow trench isolation region; removing portions of the liner while leaving a corner of the dielectric material on the shallow trench isolation regions about the top of the conductive region; removing portions of the conductive region, while maintaining the corner of the dielectric material on the shallow trench isolation region; forming a data line contact contacting the corner and coupled to a remaining portion of the conductive region after removing the portions of the conductive region; and forming a cell contact separated from the data line contact by the corner of the dielectric material.
An example method 11 of forming a memory device can include features of example method 10 of forming a memory device and can include forming the first opening to include selectively etching the sacrificial dielectric regions substantially without etching the conductive region.
An example method 12 can include features of any of the preceding example methods 10-11 of forming a memory device and can include forming the liner of dielectric material to include forming the liner by atomic layer deposition.
An example method 13 can include features of any of the preceding example methods 10-12 of forming a memory device and can include removing the portions of the liner to include performing an isotropic removal of the portions of the liner.
An example method 14 of forming a memory device can include features of example method 13 and any of the preceding example methods 10-12 of forming a memory device and can include performing the isotropic removal to include performing a wet etch of the liner.
An example method 15 of forming a memory device can include features of any of the preceding example methods 10-14 of forming a memory device and can include the dielectric material being a non-oxide dielectric.
An example method 16 of forming a memory device can include features of example method 15 and any of the preceding example methods 10-15 of forming a memory device and can include the non-oxide dielectric being one or more of a dielectric nitride or silicon carbide.
An example method 17 of forming a memory device can include features of any of the preceding example methods 10-16 of forming a memory device and can include forming the data line contact to include forming a conductive plug contacting the remaining portion of the conductive region, and forming the data line contact above and contacting the conductive plug.
An example method 18 of forming a memory device can include features of example method 15 and any of the preceding example methods of forming a memory device and can include the conductive plug being a polysilicon plug and the data line contact to include tungsten.
An example method 19 of forming a memory device can include features of any of the preceding example methods 10-18 of forming a memory device and can include the shallow trench isolation region to include a dielectric nitride.
In an example method 20 of forming a memory device, any of the example methods 12 to 19 of forming a memory device may be performed to structure an electronic memory apparatus further comprising a host processor and a communication bus extending between the host processor and the memory device.
In an example method 21 of forming a memory device, any of the example methods 12 to 20 of forming a memory device may be modified to include operations set forth in any other of method examples 12 to 20 of forming a memory device.
In an example method 22 of forming a memory device, any of the example methods 12 to 21 of forming a memory device may be modified to include operations set forth in any other of method examples 1 to 11 of forming a memory device.
In an example method 23 of forming a memory device, any of the example methods 12 to 22 of forming a memory device may be implemented at least in part through use of instructions stored as a physical state in one or more machine-readable storage devices.
An example method 24 of forming a memory device can include features of any of the preceding example methods 12 to 23 of forming a memory device and can include performing functions associated with any features of example memory devices 1 to 9.
An example memory device 1 can comprise: a memory cell having a storage element and an access device; a data line contact coupled to the access device of the memory cell; a cell contact coupled to the access device of the memory cell; a shallow trench isolation region adjacent to and contacting the data line contact; and a dielectric structure contacting the data line contact and the cell contact, the dielectric structure on and contacting the shallow trench isolation region and separating the data line contact from the cell contact.
An example memory device 2 can include features of example memory device 1 and can include the dielectric structure being a non-oxide dielectric.
An example memory device 3 can include features of example memory device 2 and features of any of the preceding example memory devices and can include the non-oxide dielectric to include one or more of a dielectric nitride or silicon carbide.
An example memory device 4 can include features of any of the preceding example memory devices and can include the data line contact being connected to a metallic data line.
An example memory device 5 can include features of any of the preceding example memory devices and can include the access device being a transistor and the storage element being a capacitor.
In an example memory device 6, any of the memory devices of example memory devices 1 to 5 may include memory devices incorporated into an electronic memory apparatus further comprising a host processor and a communication bus extending between the host processor and the memory device.
In an example memory device 7, any of the memory devices of example memory devices 1 to 6 may be modified to include any structure presented in another of example memory device 1 to 6.
In an example memory device 8, any apparatus associated with the memory devices of example memory devices 1 to 7 may further include a machine-readable storage device configured to store instructions as a physical state, wherein the instructions may be used to perform one or more operations of the apparatus.
In an example memory device 9, any of the memory devices of example memory devices 1 to 8 may be structured in accordance with any of the methods of the above example methods 1 to 24.
An example machine-readable storage device 1 storing instructions, that when executed by one or more processors, cause a machine to perform operations, can comprise instructions to perform functions associated with any features of example memory devices 1 to 9 or perform methods associated with any features of example methods 1 to 24.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Various embodiments use permutations and/or combinations of embodiments described herein. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description.
This application claims the benefit of priority to U.S. Provisional Application Ser. No. 63/402,187, filed Aug. 30, 2022, which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63402187 | Aug 2022 | US |
