Shaper circuit and shaper circuit combination

Abstract

A shaper circuit for controlling input packets using a token bucket algorithm is disclosed. The shaper circuit includes a parameter storage part for storing a current token, an add token, and a max token, a dequeue subtraction part for subtracting a packet length of a dequeue target from the current token stored in the parameter storage part and storing the current token in the parameter storage part, an add token addition part for adding the add token stored in the parameter storage part to the current token stored in the parameter storage part at constant periodic intervals and storing the current token in the parameter storage part, a max token comparison part for comparing the result of the addition of the add token addition part with the max token stored in the parameter storage part and preventing the addition result from exceeding the max token, and a dequeue permission determining part for outputting a dequeue permission request when the result of the subtraction of the dequeue subtraction part is no less than 0 and when the result of the addition of the add token addition part is no less than 0. The number of bits in each of the current token, the add token, and the max token stored in the parameter storage part are variable.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an example of a transmission apparatus;

FIG. 2 is a block diagram showing an example of a conventional shaper circuit;

FIG. 3 is a schematic diagram for describing various parameters;

FIG. 4 is a schematic diagram for describing a token bucket algorithm;

FIG. 5 is a schematic diagram showing an exemplary configuration of a shaper circuit according to a first embodiment of the present invention;

FIG. 6 is a schematic diagram for describing a current token, an add token, and a max token according to an embodiment of the present invention;

FIG. 7 is a flowchart showing a dequeue operation according to an embodiment of the present invention;

FIG. 8 is a flowchart showing a token addition operation according to an embodiment of the present invention;

FIG. 9 is a block diagram showing a shaper circuit combination according to the second embodiment of the present invention;

FIG. 10 is a schematic diagram showing an exemplary configuration of a combined processing circuit according to an embodiment of the present invention;

FIG. 11 is a schematic diagram for describing a current token, an add token, and a max token according to another embodiment of the present invention;

FIG. 12 is a flowchart showing a dequeue operation according to another embodiment of the present invention;

FIG. 13 is a flowchart showing a token addition operation according to another embodiment of the present invention;

FIG. 14 is a schematic diagram showing a determination table according to an embodiment of the present invention;

FIG. 15 is a schematic diagram for describing a leaky bucket algorithm;

FIG. 16 is a schematic diagram showing an exemplary configuration of a shaper circuit according to the third embodiment of the present invention;

FIG. 17 is a schematic diagram for describing a current token, a sub token, and a threshold according to an embodiment of the present invention;

FIG. 18 is a flowchart showing a dequeue operation according to yet another embodiment of the present invention;

FIG. 19 is a flowchart showing a token subtraction operation according to an embodiment of the present invention;

FIG. 20 is a block diagram showing a shaper circuit combination according to the fourth embodiment of the present invention;

FIG. 21 is a schematic diagram for describing a current token, a sub token, and a threshold according to another embodiment of the present invention;

FIG. 22 is a flowchart showing a dequeue operation according to a further embodiment of the present invention;

FIG. 23 is a flowchart showing a token subtraction operation according to another embodiment of the present invention; and

FIG. 24 is a schematic diagram showing a determination table according to another embodiment of the present invention.

Claims

1. A shaper circuit for controlling input packets using a token bucket algorithm, the shaper circuit comprising: a parameter storage part for storing a current token, an add token, and a max token therein;a dequeue subtraction part for subtracting a packet length of a dequeue target from the current token stored in the parameter storage part and storing the current token in the parameter storage part;an add token addition part for adding the add token stored in the parameter storage part to the current token stored in the parameter storage part at constant periodic intervals and storing the resulting current token in the parameter storage part;a max token comparison part for comparing the result of the addition of the add token addition part with the max token stored in the parameter storage part and preventing the addition result from exceeding the max token; anda dequeue permission determining part for outputting a dequeue permission request when the result of the subtraction of the dequeue subtraction part is no less than 0 and when the result of the addition of the add token addition part is no less than 0;wherein the number of bits in each of the current token, the add token, and the max token stored in the parameter storage part are variable.

2. A shaper circuit combination, the shaper circuit combination comprising: first and second shaper circuits, each shaper circuit having substantially the same configuration as the shaper circuit as claimed in claim 1; anda combined processing part connected between the first and the second shaper circuits for expanding the number of bits of the current token, the add token, and the max token stored in the parameter storage part of the first and the second shaper circuits.

3. The shaper circuit combination as claimed in claim 2, wherein the combined processing part receives a carry up signal from the add token addition part of the first shaper circuit, a carry down signal from the dequeue subtraction part of the first shaper circuit, and comparison results from each of the max token comparison parts of the first and the second shaper circuits, wherein the combined processing part includes a next length calculating part for adding the carry down signal to the packet length of the dequeue target and sending the addition result to the dequeue subtraction part of the second shaper circuit, anda next add token calculating part for adding the carry up signal to the add token in the parameter storage part of the second shaper circuit, sending the addition result to the add token addition part of the second shaper circuit, generating a signal for setting the value of the current token equal to the value of the max token according to the comparison results of the max token comparison part of the first and the second shaper circuits, and sending the signal to the first and the second shaper circuits.

4. A shaper circuit for controlling input packets using a leaky bucket algorithm, the shaper circuit comprising: a parameter storage part for storing a current token, a sub token, and a threshold therein;a dequeue length addition part for adding a packet length of a dequeue target to the current token stored in the parameter storage part and storing the added current token in the parameter storage part;a sub token subtraction part for subtracting the sub token stored in the parameter storage part from the current token stored in the parameter storage part at constant periodic intervals and storing the current token in the parameter storage part;a threshold comparison part for comparing the result of the addition of the dequeue length addition part with the threshold stored in the parameter storage part and requesting dequeue permission when the addition result is no greater than the threshold; anda dequeue permission determining part for outputting a dequeue permission request when the result of the subtraction of the sub token subtraction part is greater than 0;wherein the number of bits in each of the current token, the sub token, and the threshold stored in the parameter storage part are variable.

5. A shaper circuit combination, the shaper circuit combination comprising: first and second shaper circuits, each shaper circuit having substantially the same configuration as the shaper circuit as claimed in claim 4; anda combined processing part connected between the first and the second shaper circuits for expanding the number of bits of the current token, the sub token, and the threshold stored in the parameter storage part of the first and the second shaper circuits.

6. The shaper circuit combination as claimed in claim 5, wherein the combined processing part receives a carry up signal from the dequeue length addition part of the first shaper circuit, a carry down signal from the sub token subtraction part of the first shaper circuit, and comparison results from each of the threshold comparison parts of the first and the second shaper circuits, wherein the combined processing part includes a next length calculating part for adding the carry down signal to the packet length of the dequeue target and sending the addition result to the dequeue length addition part of the second shaper circuit, anda next add token calculating part for adding the carry up signal to the sub token in the parameter storage part of the second shaper circuit, sending the addition result to the sub token subtraction part of the second shaper circuit, generating a signal for requesting the dequeue permission according to the comparison results of the threshold comparison part of the first and the second shaper circuits, and sending the signal to the first and the second shaper circuits.