Patent Application
20170160782
Embodiments of the disclosure relate to power management in a multicore processor system.
A multicore processor system typically use a voltage regulator to supply power to its processors or clusters. A voltage regulator is designed to automatically maintain a constant voltage level. Voltage regulators are found in electronic devices such as computer power supplies, where they stabilize the DC voltages used by processors and other electronic components. Many types of voltage regulators are commonly in use, such as linear regulators and switching regulators.
Linear regulators are based on devices that operate in their linear region. A linear regulator maintains a constant output voltage by adapting its resistance to the load. The difference between the input and the regulated output voltages is dissipated as heat. Because the regulated output voltage is lower than the input voltage, efficiency of a linear regulator is limited.
By contrast, a switching regulator uses an active device that switches on and off to maintain an average value of output. Modern computers or computing devices typically use a switching regulator to supply power to its processors and other electronic components. A switching regulator is sometimes referred to as a “buck regulator,” “buck converter” or “buck.”
A multicore processor system can sometimes experience workload imbalance across its processors. Such unbalanced workload causes unbalanced demand on power among the processors. Power efficiency in such a system is of major concern.
In one embodiment, there is provided a method for improving the power consumption of a system. The system includes multiple processing units and multiple power sources, wherein each power source is connected to two or more processing units. The method comprises: detecting a condition for activating a processing unit; in response to the detected condition, identifying a power source that is connected to inactive processing units only; and activating a target processing unit among the inactive processing units connected to the identified power source.
In another embodiment, there is provided a system operative to improve power consumption. The system comprises: a plurality of processing units and a plurality of power sources. Each power source is connected to two or more processing units. The system further comprises a power manager module coupled to the processing units. The power manager module is further operative to: detect a condition for activating a processing unit among the plurality of processing units; in response to the detected condition, identify a power source that is connected to inactive processing units only; and activate a target processing unit among the inactive processing units connected to the identified power source.
The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that different references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
In the following description, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description. It will be appreciated, however, by one skilled in the art, that the disclosure may be practiced without such specific details. Those of ordinary skill in the art, with the included descriptions, will be able to implement appropriate functionality without undue experimentation.
It should be noted that the term “multicore processor system” as used herein is a system that includes multiple processors. In one embodiment, each processor is equivalent to a central processing unit (CPU), which may contain one or more cores. Alternatively, one or more of the processors may be a special-purpose processor or accelerator that contains one or more cores, which are also referred to as processing elements. The multiple processors may be arranged and managed as one or more clusters. Moreover, the term “processing unit” as used herein refers to a cluster of processors, a processor of multiple cores, or a core. The term “power source” as used herein refers to a circuitry that supplies power to one or more processing units and maintains the output voltage level supplied to the processing units. Examples of a power source include a voltage regulator such as a switching regulator (i.e., a “buck”), or a linear regulator such as a low-dropout (LDO) circuit. In one embodiment, a system may include multiple bucks, each supplying a different voltage to one or more processing units. In this embodiment, each buck is called a power source. In an alternative embodiment, each of these multiple bucks supplies its output voltage to multiple LDOs. Each LDO supplies a voltage to one or more processing units. In this alternative embodiment, each LDO is called a power source. A system may include a combination of any number of bucks and any number of LDOs.
Embodiments of the invention improve power consumption of a multicore processor system. The system includes multiple (e.g., N) processing units and multiple (e.g., M) power sources, where M and N are positive integers greater than one. Each of the M power sources may be connected to two or more processing units. In a typical low power usage scenario, the number of required processing units for handling the system workload is often less than or equal to the number of power sources (M). In one embodiment, the number of required processing units may be the same as, or a factor of, the number of parallel tasks in the workload. The number of parallel tasks in a workload is sometimes referred to as Task-Level Parallelism (TLP).
When the number of required processing units for handling the workload is less than or equal to M, for each power source, a power manager of the system activates no more than one processing unit among all processing units connected to that power source. Power efficiency and power consumption can be improved when each activated processing unit receives power from a different power source. By contrast, if multiple activated processing units draw power from the same power source and the workload among these processing units is unbalanced, the system would operate with poor power efficiency and high power consumption.
In one embodiment where the processing units 110 are of different types, some of the processing units 110 may have higher power consumption and higher processing capability than others. Those processing units 110 having similar power consumption may have different processing capabilities. In some embodiments, all of the processing units 110 may be of the same type. Each processing unit 110 has access to a system memory 130 (e.g., dynamic random access memory (DRAM) or other volatile or non-volatile random-access memory) via a bus or an interconnection network.
The processing units 110 are connected to a power source module 162 that includes a plurality of power sources 160 (e.g., PS1, PS2, PS3, . . . , PSM). Each power source 160 is connected to two or more processing units 110, and each processing unit 110 is connected to only one power source 160. In one embodiment, each power source 160 is a voltage regulator (e.g., a buck or an LDO) that provides a direct current (DC) voltage to one or more of the processing units 110. The power source 160 converts a common source voltage into one or more DC voltages that are suitable for the operations of the processing units 110.
In one embodiment, the system 100 includes a power manager module, also referred to as a power manager 121, to manage power supplied from the power sources 160 to the processing units 110. In particular, the power manager 121 may determine which processing units 110 to turn on or off in order to optimize power efficiency of the system 100. In one embodiment, the power manager 121 may be part of a kernel 120 executed on the system 100. The kernel 120 is part of an Operating System (OS) that mediates access to system resources, and is responsible for enabling user applications to effectively share the hardware by controlling access to the processors, memory, disk I/O, and network. In an alternative embodiment, the power manager 121 may be implemented by hardware, firmware, or a combination of software and hardware/firmware.
In one embodiment, the system 100 may be part of a mobile computing and/or communication device (e.g., a smartphone, a tablet, laptop, etc.). In one embodiment, the system 100 may be part of server computer.
In one embodiment, the power manager 121 determines which processing units 110 to activate and which processing units 110 to deactivate. A processing unit 110 is “activated” or, equivalently, “active” when it is turned on from a power-off state (i.e., receives no power) or an ultra-low power state (i.e., in deep sleep). Power consumed by a processing unit 110 in an ultra-low power state can be as low as to retain data in the caches but not sufficient to afford logical calculations. An activated processing unit may be actively processing tasks or may enter a standby state ready to process tasks. A processing unit 110 is “deactivated” or, equivalently, “inactive” when it enters the power-off state or the ultra-low power state.
In one embodiment, the power manager 121 also determines the required voltage for each activated processing unit 110. The required voltage is the minimum voltage for the processing unit 110 to process its assigned workload to achieve a required performance. That is, for each processing unit 110, the voltage received from its power source 160 cannot be less than its required voltage. During runtime, the required voltages of the processing units 110 may change to adapt to the fluctuation in the workload requirements of the processing units 110. In one embodiment, the power manager 121 performs dynamic frequency and voltage scaling (DVFS) on the system 100 to dynamically adjust the operating frequency and voltage of each processing unit 110 at runtime, such that its operating voltage can keep up with the changes in the required voltage.
Thus, if multiple processing units 110 having unbalanced workload share the same power source, a processing unit having a large workload would require a high operating voltage, and another processing unit having a small workload would be forced to operate at the same voltage, which is higher than its required voltage. This higher voltage results in unnecessary power consumption and power inefficiency. Therefore, the system and method described herein provide a solution to the power efficiency problem for typical usage scenarios where the number of required processing units 110 is not greater than the number of power sources 160.
The example of
In a heterogeneous processor system where there are two or more types of processing units, a power manager may determine which type of processing unit to activate based on system performance requirements, workload, power consumption, availability, among other factors. In
In an embodiment, when a condition for activating a processing unit is detected, the power manager 121 selects a power source 160 that is connected to inactive processing units only; that is, a power source 160 that is not currently supporting any other active processing units 110. The power manager 121 then activates one of the processing units 110 that are connected to the selected power source 160. The power manager 121 may repeat the selection and activation for M times, until each power source 160 in the system 100 has one activated processing unit 110.
In one embodiment, the condition for activating or deactivating a processing unit 110 may include, but are not limited to, changed workload or performance requirements. However, other predetermined condition may also exist. In one embodiment, the power manager 121 coordinates its operations with a task scheduler that is responsible for task scheduling when a new task arrives. After the power manager 121 turns on one of the processing units 110, the task scheduler may schedule the new task to that processing unit.
When a condition for deactivating a processing unit is detected, the processing units of the first type may be deactivated in the second order. If the processing units of the first type has been activated in the first order, the deactivation may start from the processing unit (of the first type) that was most recently activated. The processing units of the second type may be deactivated in the first order. If the processing units of the second type has been activated in the second order, the deactivation may start from the processing unit (of the second type) that was most recently activated.
In
The sequence of operations in
Furthermore, in this example, each processing unit is given an index consisting of two numbers. The first number indicates the processing unit's sequential order of activation. The order of deactivation is opposite to the order of activation. The second number is used to differentiate different types of the processing units. In alternative embodiments, the data structure 410 may include different indicators for conveying the information with respect to the order of activation and processor types.
The method 500 begins with arranging the power sources in a sequence (step 510). In response to a detected condition, the power manager 121 determines whether to activate or deactivate a processing unit (step 520). If the power manager 121 determines to activate, it further determines whether to activate a first processing unit or a second processing unit (step 530). Similarly, if the power manager 121 determines to deactivate, it further determines whether to deactivate a first processing unit or a second processing unit (step 540). The determination of whether to activate/deactivate a first processing unit or a second processing unit may be based on, for example, performance requirements, workload, availability, power consumption, among other factors.
If the power manager 121 determines to activate a first processing unit, one of the first processing units is activated in a first order of the sequence (step 531). The first order may be the same order as how the power sources are ordered, or may be another predetermined order. If the power manager 121 determines to activate a second processing unit, one of the second processing units is activated in a second order (step 533). The second order is reverse to the first order. A non-limiting example of the first order and the second order is shown in
If the power manager 121 determines to deactivate a first processing unit, one of the first processing units is deactivated in the second order (step 542). If the order of activation is followed in step 531, the deactivated first processing unit is the first processing unit that was most recently activated. If the power manager 121 determines to deactivate a second processing unit, one of the second processing units is deactivated in a first order (step 544). If the order of activation is followed in step 533, the deactivated second processing unit is the second processing unit that was most recently activated. After a processing unit is activated or deactivated, the method 500 may repeat from step 520 at which the power manager 121 determines whether to activate or deactivate another processing unit when a condition is detected.
The method 500 may be used to activate and deactivate processing units in a system where each power source is connected to two different types of processing units. When a power source is connected to two or more processing units of the same type or different types, a method as described below in connection with
The method 600 starts when a condition is detected for activating a processing unit (step 610). In response to the detected condition, the power manager 121 identifies a power source that is connected to inactive processing units only (step 620). The power manager 121 then activates a target processing unit among the inactive processing units connected to the identified power source (step 630). In one embodiment, the method 600 may be performed repeatedly at runtime until all power sources are connected to one activated processing unit.
In one embodiment, the detected condition may be a change in system performance requirements or workload, such that an additional or a different processing unit is needed. Other system conditions may also trigger the activation of a processing unit.
As such, the methods 500 and 600 manage power consumption by improving power efficiency when the number of required processing units is not greater than the number of power sources in a system. Moreover, the method 500 provides a technique for activating and deactivating the processing units efficiently. Therefore, power efficiency of the system can be improved or maximized.
In some scenarios where the performance requirement exceeds a threshold, a multicore processor system may activate more processing units than the number of power sources. These scenarios are performance-driven; that is, the concern for power efficient becomes secondary. The embodiments described herein are applicable to power efficiency-driven scenarios especially where the number of processing units is not greater than the number of power sources.
The operations of the flow diagrams of
While the disclosure has been described in terms of several embodiments, those skilled in the art will recognize that the disclosure is not limited to the embodiments described, and can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.
This application claims the benefit of U.S. Provisional Application No. 62/263,762 filed on Dec. 7, 2015.
| Number | Date | Country | |
|---|---|---|---|
| 62263762 | Dec 2015 | US |
