Patent Grant
11061733
The invention relates generally to digital computing system, and more particularly, to computing systems that implement computing accelerators.
Multi-core based computing systems can be used to solve a number of data and/or compute intensive problems. Computers with multiple cores can be used within a data center, server farm, or some other suitable facility. Associated with these cores may be one or more accelerators dedicated to specific computational tasks. For example, various types of accelerators can be employed including, but not limited to, an accelerator Central Processing Unit (CPU), on-chip accelerators, cryptographic accelerators, encoding/decoding accelerators, and network accelerators.
According to a non-limiting embodiment, a digital computing system is configured to control access to an accelerator. The system includes a processor that executes an application, and an accelerator that performs a data processing operation in response to an access request output from the application. The system further includes a virtual accelerator switchboard (VAS) to determine an availability of at least one shared credit corresponding to the accelerator and assign an available shared credit to the application. The application submits a request to access the accelerator using the assigned shared credit.
According to another non-limiting embodiment, a method for controlling access to an accelerator of a computer is provided. The method comprises executing, via a processor, an application, and outputting, via the application, an access request to perform a data processing operation via the accelerator. The method further comprises determining an availability of at least one shared credit corresponding to the accelerator and assigning an available shared credit to the application. The method further comprises submitting, via the application, a request to access the accelerator using the assigned credit.
According to still another non-limiting embodiment, a computer program product is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a computer processor to cause the computer processor to perform a method for controlling access to an accelerator of a computer. The method incudes executing, via a processor, an application, and outputting, via the application, an access request to perform a data processing operation via the accelerator. The method further comprises determining an availability of at least one shared credit corresponding to the accelerator and assigning an available shared credit to the application. The method further comprises submitting, via the application, a request to access the accelerator using the assigned credit.
Additional features and advantages are realized through the techniques of the invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.
The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
Various embodiments of the invention are described herein with reference to the related drawings. Alternative embodiments of the invention can be devised without departing from the scope of this invention. Various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein.
The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
Additionally, the term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms “at least one” and “one or more” may be understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms “a plurality” may be understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term “connection” may include both an indirect “connection” and a direct “connection.”
The terms “about,” “substantially,” “approximately,” and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5%, or 2% of a given value.
For the sake of brevity, conventional techniques related to making and using aspects of the invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs to implement the various technical features described herein are well known. Accordingly, in the interest of brevity, many conventional implementation details are only mentioned briefly herein or are omitted entirely without providing the well-known system and/or process details.
Turning now to an overview of technologies that are more specifically relevant to aspects of the invention, modern processors can implement an accelerator that can be accessed or invoked via a Virtual Accelerator Switchboard (VAS). In the VAS implementation, an application registers with the operating system (OS) to gain access to an accelerator. The application issues a request to access an accelerator, which is first received by the VAS. The VAS uses send windows and receive windows to transmit data (e.g., access requests, intended function data, data to be processed, etc.) between an application and a receiving accelerator. In at least one embodiment described herein, the number of requests that can be sent by an application or received by an accelerator is controlled by credits that are allocated to the send and receive window. When the send window does not have send credits or the receive window does not have receive credits, the VAS denies the exchange (e.g., the access request) between the application and the accelerator. In at least one embodiment, the system provides certain applications or high-priority applications exclusive access to accelerators in order to ensure the quality of service, while also allowing lower-priority applications to take advantage of free or available accelerator cycles using shared access of non-exclusive accelerator resources.
As described herein, one or more embodiments address the above-described shortcomings of the prior art by providing a computing system capable of controlling access to one or more accelerators by categorizing credits as either shared credits or exclusive credits. Exclusive credits aim to provide selected or predetermined high-priority applications with reserved access to an accelerator, while shared credits still allow other applications the ability to access an available or non-reserved accelerator. In this manner,
Referring now to
Bus 18 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnects (PCI) bus.
Computer system 10 may include a variety of computer system readable media. Such media may be any available media that is accessible by computer system/server 10, and it includes both volatile and non-volatile media, removable and non-removable media.
System memory 28 can include an operating system (OS) 50, along with computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and/or cache memory 32. Computer system 10 may further include other removable/non-removable, volatile/non-volatile computer system storage media. By way of example only, storage system 34 can be provided for reading from and writing to a non-removable, non-volatile magnetic media (not shown and typically called a “hard drive”). Although not shown, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a “floppy disk”), and an optical disk drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media can be provided. In such instances, each can be connected to bus 18 by one or more data media interfaces. As will be further depicted and described below, memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the disclosure.
The OS 50 controls the execution of other computer programs and provides scheduling, input-output control, file and data management, memory management, and communication control and related services. The OS 50 can also include a library API (not shown in
The storage system 34 can store a basic input output system (BIOS). The BIOS is a set of essential routines that initialize and test hardware at startup, start execution of the OS 50, and support the transfer of data among the hardware devices. When the computer system 10 is in operation, the processors 16a-16n are configured to execute instructions stored within the storage system 34, to communicate data to and from the memory 28, and to generally control operations of the computer system 10 pursuant to the instructions.
The accelerators 12a, 12b, 12n are in signal communication with each processor 16a-16n, along with the system memory 28, and can operate as a hardware accelerator. In at least one embodiment, there is a one-to-one relationship between the number of processors 16a, 16b, 16n, etc., and the number of accelerators 12a, 12b, 12n.
Each accelerator 12a, 12b, 12n can apply various computing operations including, but not limited to, compression algorithms or decompression algorithms, sometimes referred to as hardware compressions or hardware decompressions, to data or data streams requested by an application, sometimes referred to as a “process” or “thread”. Various lossless compression algorithms, for example, can be executed by the accelerator to reduce the size of data or a data stream requested by an application. Although the application is described herein in terms of issuing compression requests, the application is not limited thereto and can apply in a similar manner to decompression requests.
Program/utility 40, having a set (at least one) of program modules 42, may be stored in memory 28 by way of example, and not limitation, as well as the OS 50, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data or some combination thereof, may include an implementation of a networking environment. Program modules 42 generally carry out the functions and/or methodologies of embodiments of the invention as described herein.
Computer system 10 may also communicate with one or more external devices 14 such as a keyboard, a pointing device, a display 24, etc.; one or more devices that enable a user to interact with computer system/server 10; and/or any devices (e.g., network card, modem, etc.) that enable computer system/server 10 to communicate with one or more other computing devices. Such communication can occur via Input/Output (I/O) interfaces 22. Still yet, computer system 10 can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), and/or a public network (e.g., the Internet) via network adapter 20. As depicted, network adapter 20 communicates with the other components of computer system 10 via bus 18. It should be understood that although not shown, other hardware and/or software components could be used in conjunction with computer system 10. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data archival storage systems, etc.
The application 200 registers with the OS (not shown in
To facilitate a request to an accelerator 12a, 12b, 12n a copy instruction 256 is issued, which copies the cache-line containing the RB into a copy buffer 258. The buffered data including the RB is then output as a paste instruction 260 and serves to transfer the contents of the copy buffer to the ‘paste address’ corresponding to the RB. The paste instruction 260 is received at a first-input/first-output buffer 261, which is then delivered to an accelerator 12a, 12b, 12n associated with the EA in the paste instruction 260.
Upon completion of the request by an accelerator 12a, 12b, 12n, a memory controller (not shown) generates PB output data/parameters, a completion code indicating whether the request completed with an error or exception (zero indicates no error or exception condition) and sets a valid bit of the SB. Optionally, an interrupt notification can be sent when the RB has completed.
The VAS 202 uses send windows 262 and receive windows 264 to transmit data between an application 200 and a receiving accelerator 12a, 12b, 12n or another application (not shown). In one or more embodiments described herein, the number of access requests that can be sent and received is controlled by credits 266 and 268 that are allocated to the send and receive windows 262 and 264. If the send window 262 does not contain send credits 266 or the receive window does not contain receive credits 268, the paste command 260 will fail, i.e., will be denied by the VAS 202.
As described herein, various non-limiting embodiments provide a scheme of allocating shared credits and exclusive credits to one or more applications or processes to control access to an accelerator. Unlike conventional credit-based schemes, various embodiments described herein share credits between accelerators based on two different credit categories. That is, two different types of credits are selected from two different pools. One category of credits is reserved for exclusive applications afforded exclusive access, while the other credits are available to non-exclusive applications that can request and utilize shared credits without reserving exclusive access to an accelerator. In at least one embodiment, the categorized credits include exclusive credits and shared credits.
Exclusive credits are associated to a single accelerator dedicated to performing a particular process or function. In this manner, the application or owner running the application is always ensured access to submit work or request process from a corresponding accelerator.
Shared credits, on the other hand, refer to credits that are shared among multiple users or multiple applications. This type of credit does not ensure that work can be submitted to an accelerator, or that work or an access request will be processed or performed by an accelerator in a timely manner.
In either case, described above, each credit is mapped to a given accelerator's VAS send window. However, the credits are not shared between windows. In this manner, the system provides enhanced performance for applications with exclusive access to the accelerators while also allowing applications that do not need performance guarantees (e.g., non-exclusive applications) the ability to utilize an available shared-access accelerator.
In at least one embodiment, the VAS 202 generates a shared credit pool 300 and an exclusive credit pool 302. The shared credit pool 300 and the exclusive credit pool 302 can be an area of memory configured to store or contain data defining one or more credits. For example, one unassociated credit 304a-304n per VAS send window (1-n) is initially organized into the shared credit pool 300 (see
As applications request a shared credit 304a-304n to access an accelerator, credits are selected from the shared credit pool 300 and are associated to the application currently issuing the access request (see
In other embodiments, one or more credits in the shared pool 300 are pre-associated to an accelerator dedicated to performing a particular function. Accordingly, when an application requests access to an accelerator that performs a particular function, the system determines whether credits corresponding to the accelerator of the desired function are available. In any case, the shared credits are available to non-exclusive applications, which can request and utilize the shared credits without reserving exclusive access to an accelerator.
When there are no available credits in the shared credit pool 300, the VAS 202 or the OS (e.g., the processing unit) may revoke a shared credit from an existing process based on one or more heuristics. The heuristics include, but are not limited to, revoking the least recently used credit or taking a credit away from an application that is heavily consuming an accelerators processing resource, time of accelerator use, and number or processing request. In this manner, other applications can be provided access to the accelerators.
When a process requests exclusive access to an accelerator, the VAS 202 removes a shared credit from the shared credit pool 300 and places it into the exclusive credit pool 302. The credits transferred to the exclusive pool 302 are deemed to be exclusive credits 306f, 306g, 306h, 306i, 306j (see
An exclusive application (e.g., application D, E, F) provided with a respective exclusive credit (e.g., 306f-306j) owns the credit until it releases the accelerator window or until the desired function is completed. In at least one embodiment, exclusive credits 306f-306j are not revoked unless an accelerator is removed from the system, partition, or a virtual machine (VM).
Turning now to
When, however, the shared credit pool is empty at operation 406, the method proceeds to operation 416 and determines whether an ongoing process or application is running according to a shared credit. A shared credit is not exclusive to the running application, and therefore can be revoked by the system. When there are no applications or processes running according to a shared credit, the current access request is denied at operation 418 and the method ends at operation 420.
When, however, there are one or more applications or processes running according to a shared credit, one or more heuristic processes are performed at operation 422 to determine which shared credit to revoke and reassign. At operation 424, a shared credit is identified and is revoked from its corresponding non-exclusive application, and is transferred into the exclusive credit pool at operation 408. At operation 410, the revoked credit is re-associated to the application currently requesting exclusive access. Accordingly, the exclusive access request is deemed complete at operation 412, and the method ends at operation 414.
Returning to operation 404, the method proceeds to operation 426 when the current request is a shared access request as opposed to an exclusive access request. At this stage, a determination is made as to whether a shared access pool is empty. When the shared access pool is not empty, a shared credit is selected from the pool and associated to the application or process currently requesting access to the application at operation 428. At operation 412, the current access request is deemed complete, and the method ends at operation 414.
When, however, the shared credit pool is empty at operation 426, the method proceeds to operation 430 to determine whether an ongoing process or application is running according to a shared credit. When there are no applications or processes running according to a shared credit, the current access request is denied at operation 432 and the method ends at operation 434.
When, however, there are one or more applications or processes running according to a shared credit, one or more heuristic processes are performed at operation 436 to identify the running shared credit. At operation 438, a determination is made as to whether any of the identified shared credits can be revoked. When no revocable shared credits are available, the current access request is denied at operation 432 and the method ends at operation 434. Otherwise, the identified shared credit is revoked from the corresponding non-exclusive application at operation 440, and is re-associated to the application currently requesting the shared access at operation 428. Accordingly, the current access request is deemed complete at operation 412, and the method ends at operation 414.
Various technical benefits are achieved using the system and methods described herein, including the capability of providing enhanced performance for applications with exclusive access to the co-processors while also allowing applications that do not need performance access to accelerators when shared access is available. In this manner, the computer system can realize performance gains through the use of co-processors in the system, thereby improving overall processing speeds.
The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.
These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
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| Number | Date | Country | |
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| 20200073721 A1 | Mar 2020 | US |
